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Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
https://www.xilinx.com/ai
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DPU TRD build fails due to missing 'aie/ip/libadf.a' #1344

Closed danielstumpp closed 11 months ago

danielstumpp commented 11 months ago

I am attempting to build the DPU TRD for the vck190 using the provided Vitis flow. I have followed the README documentation in the TRD downloaded from here and have also attempted to use the build flow provided in the WAA ResNet50 example here.

I am using Vitis 2022.2 and Petalinux 2022.2 on Ubuntu 22.04.

Both of the above methods result in an error along the lines of what is attached below. The apparent error is on the second to last line: cp: cannot stat 'aie/ip/libadf.a': No such file or directory

I have confirmed that the libadf.a file does not exist. Any ideas on the cause of this? 

+ export CUR_DIR=/home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190
+ CUR_DIR=/home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190
+ cd /home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190/../../../../plugins/blobfromimage/pl
+ make cleanall
rm -rf build_dir.sw_emu.xilinx_vck190_base_202220_1/blobfromimage vitis_* TempConfig system_estimate.xtxt *.rpt .run/
rm -rf src/*.ll _xocc_* .Xil dltmp* xmltmp* *.log *.jou *.wcfg *.wdb sample_link.ini sample_compile.ini obj* bin* *.csv *.jpg *.jpeg
rm -rf build_dir.sw_emu.xilinx_vck190_base_202220_1/*.xclbin _vimage *xclbin.run_summary qemu-memory-_* emulation/ _vimage/ start_simulation.sh *.xclbin
rm -rf _x_temp.*/_x.* _x_temp.*/.Xil _x_temp.*/profile_summary.* xo_* _x*
rm -rf _x_temp.*/dltmp* _x_temp.*/kernel_info.dat _x_temp.*/*.log 
rm -rf _x_temp.* 
rm -rf build_dir.sw_emu.xilinx_vck190_base_202220_1 sd_card* build_dir.* emconfig.json *.html _x_temp.sw_emu.xilinx_vck190_base_202220_1 /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/reports *.csv *.run_summary /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/*.raw package_* run_script.sh .ipcache *.str /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/*.xo
rm -rf /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/Makefile/common/data/*.xe2xd* /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/Makefile/common/data/*.orig*
rm -rf  /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/Work /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/*.xpe /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/hw.o /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/*.xsa /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/xnwOut aiesimulator_output .AIE_SIM_CMD_LINE_OPTIONS
+ make xo TARGET=hw BLOB_CHANNEL_SWAP_EN=0 BLOB_CROP_EN=0 BLOB_LETTERBOX_EN=0 BLOB_JPEG_EN=0 BLOB_NPC=1
Compiling Kernel: blobfromimage_accel
mkdir -p _x_temp.hw.xilinx_vck190_base_202220_1
v++ -c  -t hw --platform /tools/Xilinx/Vitis/2022.2/base_platforms/xilinx_vck190_base_202220_1/xilinx_vck190_base_202220_1.xpfm --save-temps --optimize 2 --hls.jobs 8 --hls.clock 300000000:blobfromimage_accel -I/home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/../../include/pl/ -D_BLOB_CHANNEL_SWAP_EN_=0 -D_BLOB_JPEG_EN_=0  -D_BLOB_CROP_EN_=0 -D_BLOB_LETTERBOX_EN_=0 -D_BLOB_NPC_=1 -k blobfromimage_accel -I'/home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl' --temp_dir _x_temp.hw.xilinx_vck190_base_202220_1 --report_dir /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/reports/_x.hw.xilinx_vck190_base_202220_1 -o'_x_temp.hw.xilinx_vck190_base_202220_1/blobfromimage_accel.xo' /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/xf_blobfromimage_accel.cpp
Option Map File Used: '/tools/Xilinx/Vitis/2022.2/data/vitis/vpp/optMap.xml'

****** v++ v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
    Reports: /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/reports/_x.hw.xilinx_vck190_base_202220_1/blobfromimage_accel
    Log files: /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/_x_temp.hw.xilinx_vck190_base_202220_1/logs/blobfromimage_accel
Running Dispatch Server on port: 41693
INFO: [v++ 60-1548] Creating build summary session with primary output /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/_x_temp.hw.xilinx_vck190_base_202220_1/blobfromimage_accel.xo.compile_summary, at Wed Sep 27 13:10:34 2023
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/reports/_x.hw.xilinx_vck190_base_202220_1/blobfromimage_accel/v++_compile_blobfromimage_accel_guidance.html', at Wed Sep 27 13:10:34 2023
INFO: [v++ 60-895]   Target platform: /tools/Xilinx/Vitis/2022.2/base_platforms/xilinx_vck190_base_202220_1/xilinx_vck190_base_202220_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/tools/Xilinx/Vitis/2022.2/base_platforms/xilinx_vck190_base_202220_1/hw/hw.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: xilinx_vck190_base_202220_1
INFO: [v++ 60-242] Creating kernel: 'blobfromimage_accel'
INFO: [v++ 60-1616] Creating a HLS clock using hls.clock option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: blobfromimage_accel Log file: /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/_x_temp.hw.xilinx_vck190_base_202220_1/blobfromimage_accel/blobfromimage_accel/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'MMIterInLoop1'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'MMIterInLoop1'
INFO: [v++ 204-61] Pipelining loop 'MMIterInLoopRow'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 6, loop 'MMIterInLoopRow'
INFO: [v++ 204-61] Pipelining loop 'VITIS_LOOP_339_1_VITIS_LOOP_344_2'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'VITIS_LOOP_339_1_VITIS_LOOP_344_2'
INFO: [v++ 204-61] Pipelining function 'scaleCompute<17, 42, 20, 48, 16, 1>'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, function 'scaleCompute<17, 42, 20, 48, 16, 1>'
INFO: [v++ 204-61] Pipelining loop 'VITIS_LOOP_396_5'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 15, loop 'VITIS_LOOP_396_5'
INFO: [v++ 204-61] Pipelining loop 'VITIS_LOOP_115_1'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 6, loop 'VITIS_LOOP_115_1'
INFO: [v++ 204-61] Pipelining loop 'VITIS_LOOP_49_1'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'VITIS_LOOP_49_1'
INFO: [v++ 204-61] Pipelining loop 'MMIterOutRow_MMIterOutCol'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 4, loop 'MMIterOutRow_MMIterOutCol'
INFO: [v++ 204-61] Pipelining loop 'MMIterOutLoop2'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'MMIterOutLoop2'
INFO: [v++ 200-789] **** Estimated Fmax: 406.01 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/reports/_x.hw.xilinx_vck190_base_202220_1/blobfromimage_accel/system_estimate_blobfromimage_accel.xtxt
INFO: [v++ 60-586] Created _x_temp.hw.xilinx_vck190_base_202220_1/blobfromimage_accel.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl/_x_temp.hw.xilinx_vck190_base_202220_1/blobfromimage_accel.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 1m 6s
INFO: [v++ 60-1653] Closing dispatch client.
cp -f _x_temp.hw.xilinx_vck190_base_202220_1/blobfromimage_accel.xo /home/dstumpp/Documents/Vitis-AI/examples/waa/plugins/blobfromimage/pl
+ cd /home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190/vitis_prj
+ make all BLOB_ACCEL=../../../../../plugins/blobfromimage/pl
INFO:- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
INFO:Preparing files for project
make -C scripts all CU_N=1 CPB_N=32 BATCH_N=3  UBANK_IMG_N=16 UBANK_WGT_N=17 BATCH_SHRWGT_N=4 AIETOOL_VERSION=221 PSMNET_EN=0
make[1]: Entering directory '/home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190/vitis_prj/scripts'
cp -r ../../xvdpu_ip/aie       ../aie
if [ 0 -eq 1 ]; then \
    cp -r ../../xvdpu_ip/psmnet     ../aie ; \
    mv ../aie/psmnet/xo_files       ../    ; \
    rm -rf ../aie/graph_comb.cc                ; \
    rm -rf ../aie/scripts/compile_ip.csh.221; \
    mv ../aie/psmnet/graph_comb.cc  ../aie ; \
    mv ../aie/psmnet/compile_ip.csh ../aie/scripts/compile_ip.csh.221; \
fi;     
# cp -r ../../xvdpu_ip/aie             ../.
cp -r ../../xvdpu_ip/rtl/hdl         ../xvdpu/.
cp -r ../../xvdpu_ip/rtl/vitis_cfg   ../xvdpu/.
cp -r ../../xvdpu_ip/rtl/inc         ../xvdpu/.
cp -r ../../xvdpu_ip/rtl/ttcl        ../xvdpu/. 
sed -i "s/define wrp_CPB_N               .*/define wrp_CPB_N               32/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
sed -i "s/define wrp_BATCH_N             .*/define wrp_BATCH_N             3/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
sed -i "s/define wrp_BATCH_SHRWGT_N      .*/define wrp_BATCH_SHRWGT_N      4/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
sed -i "s/define wrp_UBANK_IMG_N         .*/define wrp_UBANK_IMG_N         16/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
sed -i "s/define wrp_UBANK_WGT_N         .*/define wrp_UBANK_WGT_N         17/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
sed -i "s/define wrp_LOAD_PARALLEL_IMG   .*/define wrp_LOAD_PARALLEL_IMG   2/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
sed -i "s/define wrp_SAVE_PARALLEL_IMG   .*/define wrp_SAVE_PARALLEL_IMG   2/g" ../xvdpu/vitis_cfg/vitis_cfg.vh
printf "\`define wrp_LOAD_PARALLEL_WGT   4\n"  >> ../xvdpu/vitis_cfg/vitis_cfg.vh
printf "\`define wrp_RAM_IMG_ADDR_BW     13\n" >> ../xvdpu/vitis_cfg/vitis_cfg.vh
printf "\`define wrp_RAM_WGT_ADDR_BW     13\n" >> ../xvdpu/vitis_cfg/vitis_cfg.vh
printf "\`define wrp_UBANK_IMG_MRS       0\n" >> ../xvdpu/vitis_cfg/vitis_cfg.vh
printf "\`define wrp_UBANK_WGT_MRS       0\n" >> ../xvdpu/vitis_cfg/vitis_cfg.vh
printf "\`define wrp_UBANK_BIAS          1\n" >> ../xvdpu/vitis_cfg/vitis_cfg.vh
INFO: Generate kernel.xml of DPUCVDX8G 
python kernel_xml.py 3 2 32 4 4
INFO: Generate 'xvdpu_aie_noc.cfg' 
make[1]: Leaving directory '/home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190/vitis_prj/scripts'
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INFO:Buiding libadf.a...
XILINX_VITIS_AIETOOLS=/tools/Xilinx/Vitis/2022.2/aietools source /tools/Xilinx/Vitis/2022.2/settings64.sh && make --no-print-directory -C aie ip CPB=32 BAT_NUM=3  vver=221 pl_freq=250 aie_activations_en=1 bat_sharewgt=4 
make[1]: 'ip' is up to date.
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INFO:Building DPUCVDX8G.xo for hw...
/tools/Xilinx/Vivado/2022.2/bin/vivado -mode batch -source /home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190/vitis_prj/scripts/gen_xvdpu_xo.tcl -tclargs hw/binary_container_1/DPUCVDX8G.xo DPUCVDX8G hw /tools/Xilinx/Vitis/2022.2/base_platforms/xilinx_vck190_base_202220_1/xilinx_vck190_base_202220_1.xpfm

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source /home/dstumpp/Documents/Vitis-AI/examples/waa/apps/resnet50/build_flow/DPUCVDX8G_vck190/vitis_prj/scripts/gen_xvdpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_xvdpu_kernel.tcl
WARNING: [IP_Flow 19-5101] Packaging a component with a SystemVerilog top file is not fully supported. Please refer to UG1118 'Creating and Packaging Custom IP'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'a_adi' has a dependency on the module local parameter or undefined parameter 'CONV_ADS_BW'.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/function.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_para.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/ctrl_pkt_BD_params.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/vitis_cfg.vh" from the top-level HDL file.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.2/data/ip'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI_CONTROL'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M00_IFM_AXIS'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((spirit:decode(id('MODELPARAM_VALUE.ARCH_OCP')) = 16) ? 64 : 128)" into user parameter "SHIM_IFM_DATA_BW".
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.2/data/ip'.
# if {[file exists "${xoname}"]} {
#     file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ./scripts/kernel.xml
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
WARNING: [Vivado 12-12407] VLNV in kernel.xml does not match VLNV in any of the IPs specified with the ip_directory option: xilinx.com:ip:DPUCVDX8G:0.0
INFO: [Common 17-206] Exiting Vivado at Wed Sep 27 13:11:45 2023...
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INFO:Copying libadf.a...
cp: cannot stat 'aie/ip/libadf.a': No such file or directory
make: *** [Makefile:134: hw/binary_container_1/libadf.a] Error 1
quentonh commented 11 months ago

@danielstumpp I have seen this before and was trying to help the user resolve but ultimately did not get their feedback.

image

ABS_PATH is defined by the current working directory in which the \vitis_prj\makefile is launched.

I would be inclined to go to DPUCVDX8G_VAI_v3.0\vitis_prj and then execute "make aie" to see what happens.

danielstumpp commented 11 months ago

Hi @quentonh, thanks for that suggestion. Running make aie revealed that I did not have the appropriate license file. I had to generate and install the license for AIE compilation (as directed in https://support.xilinx.com/s/article/76792?language=en_US).

After that, the build resulted in this error: nvalid device name xcvc1902-vsva2197-1LP-e-S-es1 for NOC/AIE model creation. Please swithc to using HDARPart to create the HIPDevice. I resolved that by updating the aiecompiler platform as noted in this post: https://support.xilinx.com/s/question/0D54U00006qVqWkSAK/cannot-integrate-dpu-into-vck190-critical-warning-aiecompiler-75674-the-use-of-device-name-xcvc-to-create-hipdevice-is-going-to-be-deprecated?language=en_US

Building the rest of the design now. Will close this when I confirm a successful build. Thanks for the help!

quentonh commented 11 months ago

@danielstumpp Oof! OK, it seems like we have to update the design archive to fix that problem. Thanks for highlighting it. I will look at modifying the script and get a new version uploaded.

danielstumpp commented 11 months ago

Ok, I reference design successfully built. One other note is that the PLATFORM definition in the makefile was incorrect in the downloaded TRD. When running the platform build the actual output location is $TRD_HOME/vck190_platform/platforms/xilinx_vck190_mipiRxSingle_hdmiTx_202220_1/vck190_mipiRxSingle_hdmiTx.xpfm

Thanks for the assistance @quentonh