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Xilinx / Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
https://www.xilinx.com/ai
Apache License 2.0
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Build vai_c_xir #475

Closed Uuuuuuho closed 3 years ago

Uuuuuuho commented 3 years ago

Hi, I'm working on a project of optimizing the PointPillars model on the ZCU102 board. I've studied the compilation flow by the provided document, including other architecture design of DPU core as well. As far as I know, only the partial model of PointPillars (PFE and RPN, accurately) are serialized (conversed) into *.xmodel format by script (run_quant.sh) in the demo project.

However, I can't find the source code of DPU instruction generator compiler (the Vitis-AI compiler). I guess the consistently generated DPU instructions, regardless of the input models, are not optimized for all models because of computation bound or memory bound caused by data layout, data re-usability and so.

My question is as follows.

  1. Is the Vitis-AI compiler not public so far?
  2. If it is, is there any plan you will to make it so?
  3. Is there any document explaining about DPU instruction set or compiler design?
qianglin-xlnx commented 3 years ago

Hi @Uuuuuuho

  1. Vitis-AI compiler is not public.
  2. So far as I know, there is no plan to open source Vitis-AI compiler.
  3. I'm sorry. There is no document explaining about the DPU instruction set. For compiler, you can refer to https://www.xilinx.com/html_docs/vitis_ai/1_3/compiling_model.html#ztl1570696058091
Uuuuuuho commented 3 years ago

Thanks for the quick reply.

It was really helpful!