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Xilinx / Vitis-AWS-F1-Developer-Labs

BSD 3-Clause "New" or "Revised" License
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Timeline not displayed in SDAccel #10

Open SilvanK4t1qbit opened 5 years ago

SilvanK4t1qbit commented 5 years ago

After setting the "Platform" correctly in the SDx project settings I was able to run the IDCT example in these tutorials in the current AWS FPGA Developer AMI. The only remaining problem is that the timeline is not properly displayed in SDAccel. In place of the timeline there is just blank space. When re-sizing the SDAccel window it occasionally shows up but then immediately disappears again. I tried all possible color settings when connecting through the Microsoft RDP client but the problem seems unrelated to these settings.

ThomasXilinx commented 5 years ago

This was is known problem with SDAccel 2018.2 on AWS F1, and this is why we kept the labs on 2017.4 even after the release of 2018.2. Are using 2018.2 or 2018.3?

SilvanK4t1qbit commented 5 years ago

I see, thanks for the quick response. I am on the current version of the FPGA Developer AMI (1.6.0) and it comes with SDAccel release 2018.3.