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make zc706 platform failed #15

Closed doonny closed 4 years ago

doonny commented 4 years ago

I am trying to make the zc706 platform, but the following error shows up:

make -C vivado PLATFORM=xilinx_zc706_base_202010_1
make[1]: Entering directory '/home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado'
mkdir -p ../platform_repo/tmp/vivado
/home/fpga/Xilinx/Vivado/2020.1/bin/vivado -mode batch -notrace -source xilinx_zc706_base_202010_1_xsa.tcl

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source xilinx_zc706_base_202010_1_xsa.tcl -notrace
INFO: [BD_TCL-3] Currently there is no design <zc706_base> in project, so creating one...
Wrote  : </home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_vivado/zc706_base. srcs/sources_1/bd/zc706_base/zc706_base.bd>
INFO: [BD_TCL-4] Making design <zc706_base> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zc706_base".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:  xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_vip:1.1 x ilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:xlconcat:2.1  .
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '10.000' to '20.000' has been  ignored for IP 'clk_wiz_0'
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-1306] The connection to interface pin /axi_intc_0/irq is being overridden by the user. This pin will not be connected as  a part of interface connection interrupt
Slave segment '/ps7/S_AXI_HP0/HP0_DDR_LOWOCM' is being assigned into address space '/axi_vip_0/Master_AXI' at <0x0000_0000 [ 1G ]>.
Slave segment '/axi_intc_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x7000_0000 [ 64K ]>.
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block!
WARNING: [xilinx.com:ip:axi_intc:4.1-4] /axi_intc_0: Could not determine interrupt input port type - using default interrupt type Rising  Edge. Please change this manually if necessary.
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not  connected to a matching interface. Please consider selecting Single instead.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
Wrote  : </home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_vivado/zc706_base. srcs/sources_1/bd/zc706_base/zc706_base.bd>
INFO: [BD 41-1662] The design 'zc706_base.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_viv ado/zc706_base.srcs/sources_1/bd/zc706_base/synth/zc706_base.v
VHDL Output written to : /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_viv ado/zc706_base.srcs/sources_1/bd/zc706_base/sim/zc706_base.v
VHDL Output written to : /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_viv ado/zc706_base.srcs/sources_1/bd/zc706_base/hdl/zc706_base_wrapper.v
INFO: [BD 41-1662] The design 'zc706_base.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_viv ado/zc706_base.srcs/sources_1/bd/zc706_base/synth/zc706_base.v
VHDL Output written to : /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_viv ado/zc706_base.srcs/sources_1/bd/zc706_base/sim/zc706_base.v
VHDL Output written to : /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_viv ado/zc706_base.srcs/sources_1/bd/zc706_base/hdl/zc706_base_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_vip_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Pl atforms/zc706_base/vivado/zc706_base_vivado/zc706_base.srcs/sources_1/bd/zc706_base/ip/zc706_base_auto_pc_0/zc706_base_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block interconnect_axifull/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Pl atforms/zc706_base/vivado/zc706_base_vivado/zc706_base.srcs/sources_1/bd/zc706_base/ip/zc706_base_auto_us_0/zc706_base_auto_us_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block interconnect_axifull/s00_couplers/auto_us .
INFO: [BD 41-1029] Generation completed for the IP Integrator block interrupt_concat/xlconcat_interrupt_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_100MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_142MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_166MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_200MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_41MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_50MHz .
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Pl atforms/zc706_base/vivado/zc706_base_vivado/zc706_base.srcs/sources_1/bd/zc706_base/ip/zc706_base_auto_pc_1/zc706_base_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_axi_periph/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
Exporting to file /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_vivado/zc7 06_base.srcs/sources_1/bd/zc706_base/hw_handoff/zc706_base.hwh
Generated Block Design Tcl file /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_b ase_vivado/zc706_base.srcs/sources_1/bd/zc706_base/hw_handoff/zc706_base_bd.tcl
Generated Hardware Definition File /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc70 6_base_vivado/zc706_base.srcs/sources_1/bd/zc706_base/synth/zc706_base.hwdef
generate_target: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2177.227 ; gain = 13.000 ; free physical = 113576 ;  free virtual = 248613
[Wed Aug 12 16:55:55 2020] Launched zc706_base_axi_vip_0_0_synth_1, zc706_base_clk_wiz_0_0_synth_1, zc706_base_proc_sys_reset_200MHz_0_sy nth_1, zc706_base_proc_sys_reset_100MHz_0_synth_1, zc706_base_proc_sys_reset_41MHz_0_synth_1, zc706_base_auto_pc_0_synth_1, zc706_base_pr oc_sys_reset_166MHz_0_synth_1, zc706_base_proc_sys_reset_50MHz_0_synth_1, zc706_base_auto_us_0_synth_1, zc706_base_proc_sys_reset_142MHz_ 0_synth_1, zc706_base_axi_intc_0_0_synth_1, zc706_base_ps7_0_synth_1, zc706_base_auto_pc_1_synth_1, synth_1...
Run output will be captured here:
zc706_base_axi_vip_0_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_b ase_vivado/zc706_base.runs/zc706_base_axi_vip_0_0_synth_1/runme.log
zc706_base_clk_wiz_0_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_b ase_vivado/zc706_base.runs/zc706_base_clk_wiz_0_0_synth_1/runme.log
zc706_base_proc_sys_reset_200MHz_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vi vado/zc706_base_vivado/zc706_base.runs/zc706_base_proc_sys_reset_200MHz_0_synth_1/runme.log
zc706_base_proc_sys_reset_100MHz_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vi vado/zc706_base_vivado/zc706_base.runs/zc706_base_proc_sys_reset_100MHz_0_synth_1/runme.log
zc706_base_proc_sys_reset_41MHz_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/viv ado/zc706_base_vivado/zc706_base.runs/zc706_base_proc_sys_reset_41MHz_0_synth_1/runme.log
zc706_base_auto_pc_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_bas e_vivado/zc706_base.runs/zc706_base_auto_pc_0_synth_1/runme.log
zc706_base_proc_sys_reset_166MHz_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vi vado/zc706_base_vivado/zc706_base.runs/zc706_base_proc_sys_reset_166MHz_0_synth_1/runme.log
zc706_base_proc_sys_reset_50MHz_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/viv ado/zc706_base_vivado/zc706_base.runs/zc706_base_proc_sys_reset_50MHz_0_synth_1/runme.log
zc706_base_auto_us_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_bas e_vivado/zc706_base.runs/zc706_base_auto_us_0_synth_1/runme.log
zc706_base_proc_sys_reset_142MHz_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vi vado/zc706_base_vivado/zc706_base.runs/zc706_base_proc_sys_reset_142MHz_0_synth_1/runme.log
zc706_base_axi_intc_0_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_ base_vivado/zc706_base.runs/zc706_base_axi_intc_0_0_synth_1/runme.log
zc706_base_ps7_0_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_vi vado/zc706_base.runs/zc706_base_ps7_0_synth_1/runme.log
zc706_base_auto_pc_1_synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_bas e_vivado/zc706_base.runs/zc706_base_auto_pc_1_synth_1/runme.log
synth_1: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706_base_vivado/zc706_base.r uns/synth_1/runme.log
[Wed Aug 12 16:55:55 2020] Launched impl_1...
Run output will be captured here: /home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado/zc706 _base_vivado/zc706_base.runs/impl_1/runme.log
[Wed Aug 12 16:55:55 2020] Waiting for impl_1 to finish...
[Wed Aug 12 16:56:07 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'zc706_base_axi_vip_0_0_synth_1', 'zc706_base_clk_wiz_0_0_synth_1', 'zc706_base_proc_sys_reset_ 200MHz_0_synth_1', 'zc706_base_proc_sys_reset_100MHz_0_synth_1', 'zc706_base_proc_sys_reset_41MHz_0_synth_1', 'zc706_base_auto_pc_0_synth _1', 'zc706_base_proc_sys_reset_166MHz_0_synth_1', 'zc706_base_proc_sys_reset_50MHz_0_synth_1', 'zc706_base_auto_us_0_synth_1', 'zc706_ba se_proc_sys_reset_142MHz_0_synth_1', 'zc706_base_axi_intc_0_0_synth_1', 'zc706_base_ps7_0_synth_1', 'zc706_base_auto_pc_1_synth_1'
wait_on_run: Time (s): cpu = 00:01:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2473.367 ; gain = 0.000 ; free physical = 113526 ; free  virtual = 248580
INFO: [Vivado 12-4895] Creating Hardware Platform: ./xilinx_zc706_base_202010_1.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (/home/fpga/Xilinx/Vivado/2020.1/data/embeddedsw) loading 1 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:23 ; elapsed = 00:00:05 . Memory (MB): peak = 2544.223 ; gain = 70.855 ; free physical = 113462  ; free virtual = 248574
ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream. Aborting write_hw_platform..
INFO: [Common 17-206] Exiting Vivado at Wed Aug 12 16:56:14 2020...
Makefile:8: recipe for target 'hw' failed
make[1]: *** [hw] Error 1
make[1]: Leaving directory '/home/fpga/Work/xilinx/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zc706_base/vivado'
Makefile:18: recipe for target 'xsa' failed
make: *** [xsa] Error 2
evilidol commented 3 years ago

same error in zcu102 platform, have you slove it?