Xilinx / Vitis_Embedded_Platform_Source

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About the Interrupt Configuration #23

Closed doonny closed 3 years ago

doonny commented 3 years ago

Hi, the Official Embedded Platform (https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/master/Xilinx_Official_Platforms/xilinx_zc706_base), the interrupt part created a concat module and explicitly created 32 input interrupt signals like follow:

捕获

But the custom platform creation tutorial (zcu104 board), step 1 Adding Interrupt Support (https://github.com/Xilinx/Vitis-In-Depth-Tutorial/blob/master/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104/step1.md), the tutorial only added an single AXI interrupt Controller without any concat module, and set the number of input intr to 1 (auto), but in the following PFM_IRQ setting, it used 32 inputs:

set_property PFM.IRQ {intr {id 0 range 32}} [get_bd_cells /axi_intc_0]

My question is : Can this concat module be removed in the zc706 platform configuration as did in the custom platform creation tutorial did? Will v++ automatically connect what is needed without explicitly create 32 input interrupt signals ?

doonny commented 3 years ago

Has got the answer