Xilinx / Vitis_Libraries

Vitis Libraries
https://docs.xilinx.com/r/en-US/Vitis_Libraries
Apache License 2.0
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Bad Synthesis Report #206

Closed losepatience closed 2 months ago

losepatience commented 2 months ago

Hi. I synthesized the following code with vitis2024.1, and the synthesis report is beyond my comprehension. The "latency" seems too big. Is this a bug of 2024.1? It's OK in 2022.02.

void crop(hls::stream<ap_axiu<192, 1, 1, 1> >& src, hls::stream<ap_axiu<192, 1, 1, 1> >& dst, int rows, int cols) {
// clang-format off
#pragma HLS INTERFACE axis port=src
#pragma HLS INTERFACE axis port=dst
#pragma HLS INTERFACE s_axilite port=rows               
#pragma HLS INTERFACE s_axilite port=cols               
#pragma HLS INTERFACE s_axilite port=return
    // clang-format on

    xf::cv::Mat<XF_8UC3, ROWS, COLS, XF_NPPC8, 3> src_mat(rows, cols);
    //xf::cv::Mat<XF_8UC3, ROWS, COLS, XF_NPPC8> dst_mat(rows, cols);
// clang-format off
#pragma HLS dataflow
    // clang-format on
    xf::cv::AXIvideo2xfMat<192,XF_8UC3, ROWS, COLS, XF_NPPC8, 3>(src, src_mat);
    xf::cv::xfMat2AXIvideo<192,XF_8UC3, ROWS, COLS, XF_NPPC8, 3>(src_mat, dst);

    return;
}
losepatience commented 2 months ago
    if (cols > COLS)
        cols = COLS;
    if (rows > ROWS)
        rows = COLS;