Closed Ali-Flt closed 4 years ago
I meet the same problem, could this bug be fixed as soon as possible?
After waiting for the Xilinx Employees for a fix and not receiving even a comment, I've tried to fix the function myself. I tested it in Csim and in hardware implementation and it seems to be working. What I basically did was merging the loop_wait_for_start and loop_height in a single loop. I've attached the modified "xf_infra.hpp" file.
Note: Additionally I've noticed that the structs defined in "xf_axi_sdata.hpp" are not getting synthesized correctly either :))
so I included
@Ali-Flt thanks for you answer, after test you code, I can build this function with "dataflow". but I met some question after load as hardware,https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/K2K-AXIvideo2xfMat-not-worked/td-p/1145308, did you met this problem.
Hi @canonant , Unfortunately I have never worked with SDAccel and have no Idea what your problem might be, But I will share the code of my Core and C Test bench, in which I used this function, and maybe it will give you an idea about what the issue might be. I doubt that your problem is from the AXIvideo2xfMat because I tested my modified function in design and in worked properly in Linux Userspace. simple_erosion.zip
Hi @Ali-Flt / @canonant We have reproduced this issue, and have a candidate fix which is under testing. We expect the fix to be published by 9/11.
Issue fixed.
Hi, I'm trying to use xf::cv::AXIvideo2xfMat and there seem to be a bug inside the code causing the synthesizer to error. the error is as followed:
I think it is because the stream input is being read in two different loops in the function code in xf_infra.hpp file. (loop_wait_for_start and loop_height)
a link to this problem in Xilinx forums: https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/HLS-failed-dataflow-checking/td-p/1049741 can you please fix this issue cause I really need this function for my work.
thanks Ali