Can't build a simple vision/L2 example

vmayoral commented 3 years ago

Trying now quickly the examples aimed for Vitis (instead of for HLS which fail, refer to https://github.com/Xilinx/Vitis_Libraries/issues/79) described in the instructions.

Using in particular resize:

source /tools/Xilinx/Vitis/2020.2/settings64.sh
export DEVICE=/home/xilinx/ros2_ws/acceleration/firmware/select/platform/kv260_base.xpfm
export SYSROOT=/home/xilinx/ros2_ws/install/../acceleration/firmware/kv260/sysroots/aarch64-xilinx-linux
export EDGE_COMMON_SW=/home/xilinx/ros2_ws/acceleration/firmware/select
#export PERL=<path-to-perl-installation-location> #For example, "export PERL=/usr/bin/perl".

make host xclbin TARGET=sw_emu HOST_ARCH=aarch64

Makefile:74: [WARNING]: This project has not been tested for /home/xilinx/ros2_ws/acceleration/firmware/select/platform/kv260_base.xpfm. It may or may not work.
mkdir -p build_dir.sw_emu.kv260_base
/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -o build_dir.sw_emu.kv260_base/resize /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/xf_resize_tb.cpp /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/build -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/ -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/include -D SW_EMU_TEST -I/opt/xilinx/xrt/include -I/tools/Xilinx/Vivado/2020.2/include -std=c++11 -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -fmessage-length=0 -O3 -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/src/  -lopencv_videoio -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_features2d -lopencv_flann -lopencv_video -lopencv_calib3d -lopencv_highgui -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -Wno-unused-label -Wno-narrowing -DVERBOSE
In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/xf_resize_tb.cpp:17:
/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:23:10: fatal error: opencv2/opencv.hpp: No such file or directory
   23 | #include "opencv2/opencv.hpp"
      |          ^~~~~~~~~~~~~~~~~~~~
compilation terminated.
In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp:33:
/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:45:10: fatal error: CL/cl2.hpp: No such file or directory
   45 | #include <CL/cl2.hpp> //"/opt/intel/opencl-1.2-4.4.0.117/include/CL/cl.h"
      |          ^~~~~~~~~~~~
compilation terminated.

vmayoral commented 3 years ago

These first few hurdles, in my case, can be bypassed with:

CXXFLAGS += -I/home/xilinx/ros2_ws/acceleration/firmware/select/sysroots/aarch64-xilinx-linux/usr/include
LDFLAGS += -L/home/xilinx/ros2_ws/acceleration/firmware/select/sysroots/aarch64-xilinx-linux/usr/lib

Which leads to further issues, so I'm stopping here and asking for support. AFAIK this should work out of the box, but it doesn't. Am I wrong somewhere? Otherwise, please clarify how to get this right.

vmayoral commented 3 years ago

make host xclbin TARGET=sw_emu HOST_ARCH=aarch64

For the record, I tried other targets, this is not a target's issue.

vt-lib-support commented 3 years ago

Hi @vmayoral ,

Few of the platforms specific flags as in here in all the Makefiles are set based on the platform. And, the current format of the Makefiles will have these flags set only for the platforms that are listed in the "platform_whitelist" section of the description.json file, as those platforms only have been tested to work. (A warning appears mentioning that it may or may not work for other platforms other than what were tested, as you can see in your posted log)

Hence if the build is targeted for a different platform, as in your case, these flags need to be manually set in the Makefile and the build is expected to work fine. Please try this and let us know (attaching the log) if issue still persists.

vt-lib-support commented 3 years ago

This issue is also reported here #43 and we are working on removing this limitation from the Makefiles.

vmayoral commented 3 years ago

Few of the platforms specific flags as in here in all the Makefiles are set based on the platform.

@vt-lib-support, this points to 2021.1 release. As pointed out, this is connected to https://github.com/Xilinx/Vitis_Libraries/issues/79 which targets 2020.2 (expecting it to be more mature and stable).

Nevertheless, here's my attempt targeting the ZCU102 (which is listed as supported) on a plain new terminal:

source /tools/Xilinx/Vitis/2020.2/settings64.sh
export DEVICE=/home/xilinx/ros2_ws/acceleration/firmware/zcu102/platform/xilinx_zcu102_base_202020_1.xpfm
export SYSROOT=/home/xilinx/ros2_ws/acceleration/firmware/zcu102/sysroots/aarch64-xilinx-linux
export EDGE_COMMON_SW=/home/xilinx/ros2_ws/acceleration/firmware/zcu102

make host xclbin TARGET=sw_emu HOST_ARCH=aarch64

```bash xilinx@xilinx:~/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize$ make host xclbin TARGET=sw_emu HOST_ARCH=aarch64 Cannot find OpenCV include path. Please set OPENCV_INCLUDE variable make: *** [Makefile:216: check_env] Error 1 ```

This leads to instructions missing in the README @vt-lib-support.

I'll try and get a complete setup running by setting the embedded variables right next.

vmayoral commented 3 years ago

After a while on this, I gave up. There're simply too many things that need to be modified for this to be a useful blueprint at 2020.2, including a merge with the new makefile logic provided in future releases as hinted in here.

I unfortunately don't have more time to help with this but I encourage a huge re-consideration of the instructions provided and build logic (Makefiles essentially).

After various modifications in the source code, and in the build system provided (I essentially discarded Makefiles and built a complete new CMakeLists.txt file that allowed me to integrate resize into other projects I managed to build), I managed to build things successfully, including the kernel. I will probably disclose this source code at a later stage, in a different repository (it needs further work), but ping me if anyone needs access to this immediately.

On a side note, @vt-lib-support please consider the input in here. As is, with 2020.2, the content in here has very limited usefulness, and I doubt users will be willing to fight and struggle a weekend like me just to get a hello world (vision) demo running. Also, I'd highly encourage to set up a public facing CI system that clears all possible doubt. Meaning, complaints like this could be referred to a CI build log which systematically shows evidence that things build indeed with the proper setup. Even better, I'd love to see such builds dockerized, so I don't need to spend hours ensuring my system is "as expected" by whoever designed this.

The need for dockerized systematic builds across Xilinx's organization's examples is a huge need identified that I very much encourage.

Edit: I'm still interested in getting HLS capabilities to work, so I'd appreciate insights on https://github.com/Xilinx/Vitis_Libraries/issues/79#issuecomment-908154056.

kapoor7997 commented 2 years ago

Hi,

I am facing the same issue with exact hardware zcu102 and libraries. Can you please provide solution if you have one.

Thanks, kapoor7997

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

Please post your error and the steps you used for the build.

kapoor7997 commented 2 years ago

I followed the same steps as vmayoral and got the same error. The error I get is steps: source /tools/Xilinx/Vitis/2020.2/settings64.sh export DEVICE=/home/xilinx/ros2_ws/acceleration/firmware/select/platform/kv260_base.xpfm export SYSROOT=/home/xilinx/ros2_ws/install/../acceleration/firmware/kv260/sysroots/aarch64-xilinx-linux export EDGE_COMMON_SW=/home/xilinx/ros2_ws/acceleration/firmware/select export PERL= #For example, "export PERL=/usr/bin/perl". make host xclbin DEVICE=zcu102 TARGET=hw HOST_ARCH=aarch64

Error: Makefile:74: [WARNING]: This project has not been tested for /home/xilinx/ros2_ws/acceleration/firmware/select/platform/kv260_base.xpfm. It may or may not work. mkdir -p build_dir.sw_emu.kv260_base /tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -o build_dir.sw_emu.kv260_base/resize /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/xf_resize_tb.cpp /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/build -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/ -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/include -D SW_EMU_TEST -I/opt/xilinx/xrt/include -I/tools/Xilinx/Vivado/2020.2/include -std=c++11 -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -fmessage-length=0 -O3 -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/src/ -lopencv_videoio -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_features2d -lopencv_flann -lopencv_video -lopencv_calib3d -lopencv_highgui -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -Wno-unused-label -Wno-narrowing -DVERBOSE In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize/xf_resize_tb.cpp:17: /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:23:10: fatal error: opencv2/opencv.hpp: No such file or directory 23 | #include "opencv2/opencv.hpp" | ^~~~~~~~ compilation terminated. In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp:33: /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:45:10: fatal error: CL/cl2.hpp: No such file or directory 45 | #include <CL/cl2.hpp> //"/opt/intel/opencl-1.2-4.4.0.117/include/CL/cl.h" | ^~~~ compilation terminated.

Plese do the needful on that, I need support from the community. IT would be really appriciated if you can provide exact steps to create images and how I can use vitis vision library L2 demo om zcu102 board.

Thanks, kapoor7997

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

We see that you intend to build the function for zcu102 but have set the DEVICE to kv260 which looks incorrect.

Please follow the steps mentioned in the Embedded Devices section of this README on how to get the required platform and follow the steps mentioned there to install sysroot.

kapoor7997 commented 2 years ago

Hi vt-lib-support,

In previous comment we just copied comments from the vmayoral as we observed the same error while building vitis vision library demo. Please find below mentioned actual error logs and steps which we followed from the README file which you have shared:

we are trying to run the Vitis Vision Library color detection demo.

Steps we followed on command prompt:

source /tools/Xilinx/Vitis/2020.2/settings64.sh source /opt/xilinx/xrt/setup.sh export DEVICE=/home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm

source /opt/xilinx/xrt/setup.sh export DEVICE=/home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm export SYSROOT=/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/images/linux/sysroots/aarch64-xilinx-linux/ export EDGE_COMMON_SW=/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/images/linux/ export OPENCV_INCLUDE=/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/image/linux/sysroots/aarch64-xilinx-linux/usr/include export OPENCV_LIB=/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/image/linux/sysroots/aarch64-xilinx-linux/usr/libe export PERL=/usr/bin/perl make host xclbin TARGET=hw DEVICE=zcu102 HOST_ARCH=aarch64

Our Console Output:

dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ make host xclbin TARGET=hw DEVICE=zcu102 HOST_ARCH=aarch64 mkdir -p build_dir.sw_emu.zcu102 /tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -o build_dir.sw_emu.zcu102/ccm /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_tb.cpp /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -DSDSVHLS -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/build -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/ -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include -D SW_EMU_TEST -I/opt/xilinx/xrt/include -I/tools/Xilinx/Vivado/2020.2/include -std=c++11 -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -fmessage-length=0 -O3 -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/src/ -lopencv_videoio -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_features2d -lopencv_flann -lopencv_video -lopencv_calib3d -lopencv_highgui -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -Wno-unused-label -Wno-narrowing -DVERBOSE In file included from /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_tb.cpp:16: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:23:10: fatal error: opencv2/opencv.hpp: No such file or directory 23 | #include "opencv2/opencv.hpp" | ^~~~~~~~ compilation terminated. In file included from /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp:33: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:45:10: fatal error: CL/cl2.hpp: No such file or directory 45 | #include <CL/cl2.hpp> //"/opt/intel/opencl-1.2-4.4.0.117/include/CL/cl.h" | ^~~~ compilation terminated. Makefile:231: recipe for target 'build_dir.sw_emu.zcu102/ccm' failed make: *** [build_dir.sw_emu.zcu102/ccm] Error 1

I have attached snapshots confirming that the opencv exists in the usr/include and usr/lib of the sysroot that I generated from my petalinux project.

It will be really appreciated if you can share any pre built images for vitis color detection demo or any kind of image processing demo for zcu102. We just wanna figure our what environment settings do we need so we can then write our actual code. We are not sure why opencv is not being detected for us.

Thanks, Kapoor7997

opencv_usr_lib opencv_usr_include

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

Since you are already setting the DEVICE as env variable pointing to your platform xpfm file, there is no need to set it again with the make command. So your build command should be: make xclbin host TARGET=hw HOST_ARCH=aarch64

Also, as your platform seems to be custom built (not among the one in _platformwhitelist of description.json), please add the following flags in the Makefile:

CXXFLAGS += -I$(SYSROOT)/usr/include
CXXFLAGS += --sysroot=$(SYSROOT)
LDFLAGS += -L$(SYSROOT)/usr/lib
LDFLAGS += -L${SYSROOT}/opt/xilinx/xrt/lib

kapoor7997 commented 2 years ago

I was using the command as mentioned in the README you chared, which is- make host xclbin TARGET=hw HOST_ARCH=aarch64 But when I used the command you gave in your answer, which is- make xclbin host TARGET=hw HOST_ARCH=aarch64 the opencv error goes away But I get the same error whether I add the CXXFLAGS or I dont. I have both the outputs in the following text:

README command dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ make host xclbin TARGET=hw HOST_ARCH=aarch64 Makefile:76: [WARNING]: This project has not been tested for /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm. It may or may not work. mkdir -p build_dir.hw.ouropencvplatform5 /tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -o build_dir.hw.ouropencvplatform5/ccm /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_tb.cpp /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -DSDSVHLS -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/build -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/ -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include -I/opt/xilinx/xrt/include -I/tools/Xilinx/Vivado/2020.2/include -std=c++11 -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -fmessage-length=0 -O3 -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/src/ -lopencv_videoio -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_features2d -lopencv_flann -lopencv_video -lopencv_calib3d -lopencv_highgui -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -Wno-unused-label -Wno-narrowing -DVERBOSE In file included from /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_tb.cpp:16: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:23:10: fatal error: opencv2/opencv.hpp: No such file or directory 23 | #include "opencv2/opencv.hpp" | ^~~~~~~~ compilation terminated. In file included from /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp:33: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:45:10: fatal error: CL/cl2.hpp: No such file or directory 45 | #include <CL/cl2.hpp> //"/opt/intel/opencl-1.2-4.4.0.117/include/CL/cl.h" | ^~~~ compilation terminated. Makefile:238: recipe for target 'build_dir.hw.ouropencvplatform5/ccm' failed make: *** [build_dir.hw.ouropencvplatform5/ccm] Error 1

Your Command dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ make xclbin host TARGET=hw HOST_ARCH=aarch64 Makefile:76: [WARNING]: This project has not been tested for /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm. It may or may not work. Compiling Kernel: ccm_accel mkdir -p _x_temp.hw.ouropencvplatform5 v++ -c -t hw --platform /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm --save-temps --optimize 2 --jobs 8 -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include/ -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/build -k ccm_accel -I'/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix' --temp_dir _x_temp.hw.ouropencvplatform5 --report_dir /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/reports/_x.hw.ouropencvplatform5 -o'_x_temp.hw.ouropencvplatform5/ccm_accel.xo' '/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_accel.cpp' WARNING: [v++ 60-1600] The option 'jobs' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'hls.jobs', 'vivado.synth.jobs' in a configuration file. Option Map File Used: '/tools/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at: Reports: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/reports/_x.hw.ouropencvplatform5/ccm_accel Log files: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/logs/ccm_accel Running Dispatch Server on port:44029 INFO: [v++ 60-1548] Creating build summary session with primary output /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel.xo.compile_summary, at Wed Feb 16 10:26:00 2022 INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Feb 16 10:26:00 2022 Running Rule Check Server on port:34819 INFO: [v++ 60-1315] Creating rulecheck session with output '/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/reports/_x.hw.ouropencvplatform5/ccm_accel/v++_compile_ccm_accel_guidance.html', at Wed Feb 16 10:26:01 2022 INFO: [v++ 60-895] Target platform: /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/hw/xilinx_zcu102_base_202020_1.xsa' INFO: [v++ 60-585] Compiling for hardware target INFO: [v++ 60-423] Target device: ouropencvplatform5 INFO: [v++ 60-242] Creating kernel: 'ccm_accel' WARNING: /tools/Xilinx/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.

===>The following messages were generated while performing high-level synthesis for kernel: ccm_accel Log file: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log : INFO: [v++ 204-61] Pipelining loop 'MMIterInLoop1'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'MMIterInLoop1' INFO: [v++ 204-61] Pipelining loop 'MMIterInLoopRow'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'MMIterInLoopRow' INFO: [v++ 204-61] Pipelining loop 'VITIS_LOOP_136_1'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 1, loop 'VITIS_LOOP_136_1' INFO: [v++ 204-61] Pipelining loop 'colLoop'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 6, loop 'colLoop' INFO: [v++ 204-61] Pipelining loop 'MMIterOutRow_MMIterOutCol'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'MMIterOutRow_MMIterOutCol' INFO: [v++ 204-61] Pipelining loop 'MMIterOutLoop2'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'MMIterOutLoop2' INFO: [v++ 200-789] * Estimated Fmax: 205.47 MHz ERROR: [v++ 213-28] Failed to generate IP. ERROR: [v++ 60-300] Failed to build kernel(ip) ccm_accel, see log for details: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log ERROR: [v++ 60-773] In '/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log', caught Tcl error: ERROR: [IMPL 213-28] Failed to generate IP. ERROR: [v++ 60-599] Kernel compilation failed to complete ERROR: [v++ 60-592] Failed to finish compilation INFO: [v++ 60-1653] Closing dispatch client. Makefile:226: recipe for target '_x_temp.hw.ouropencvplatform5/ccm_accel.xo' failed make: [_x_temp.hw.ouropencvplatform5/ccm_accel.xo] Error 1

Now With the CXXFLAGS you mentioned dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ vi Makefile dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ vi Makefile dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ README command make host xclbin TARGET=hw HOST_ARCH=aarch64 Makefile:76: [WARNING]: This project has not been tested for /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm. It may or may not work. mkdir -p build_dir.hw.ouropencvplatform5 /tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -o build_dir.hw.ouropencvplatform5/ccm /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_tb.cpp /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -DSDSVHLS -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/build -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/ -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include -I/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/images/linux/sysroots/aarch64-xilinx-linux//usr/include --sysroot=/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/images/linux/sysroots/aarch64-xilinx-linux/ -I/opt/xilinx/xrt/include -I/tools/Xilinx/Vivado/2020.2/include -std=c++11 -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -fmessage-length=0 -O3 -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/src/ -L/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/images/linux/sysroots/aarch64-xilinx-linux//usr/lib -L/home/dev/petali/opencv_build/xilinx-zcu102-2020.2/images/linux/sysroots/aarch64-xilinx-linux//opt/xilinx/xrt/lib -lopencv_videoio -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_features2d -lopencv_flann -lopencv_video -lopencv_calib3d -lopencv_highgui -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -Wno-unused-label -Wno-narrowing -DVERBOSE In file included from /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_tb.cpp:17: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:45:10: fatal error: CL/cl2.hpp: No such file or directory 45 | #include <CL/cl2.hpp> //"/opt/intel/opencl-1.2-4.4.0.117/include/CL/cl.h" | ^~~~ compilation terminated. In file included from /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp:33: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:45:10: fatal error: CL/cl2.hpp: No such file or directory 45 | #include <CL/cl2.hpp> //"/opt/intel/opencl-1.2-4.4.0.117/include/CL/cl.h" | ^~~~ compilation terminated. Makefile:238: recipe for target 'build_dir.hw.ouropencvplatform5/ccm' failed make: *** [build_dir.hw.ouropencvplatform5/ccm] Error 1

YOUR command dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ make xclbin host TARGET=hw HOST_ARCH=aarch64 Makefile:76: [WARNING]: This project has not been tested for /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm. It may or may not work. Compiling Kernel: ccm_accel mkdir -p _x_temp.hw.ouropencvplatform5 v++ -c -t hw --platform /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm --save-temps --optimize 2 --jobs 8 -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L1/include/ -I/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/build -k ccm_accel -I'/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix' --temp_dir _x_temp.hw.ouropencvplatform5 --report_dir /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/reports/_x.hw.ouropencvplatform5 -o'_x_temp.hw.ouropencvplatform5/ccm_accel.xo' '/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/xf_ccm_accel.cpp' WARNING: [v++ 60-1600] The option 'jobs' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'hls.jobs', 'vivado.synth.jobs' in a configuration file. Option Map File Used: '/tools/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at: Reports: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/reports/_x.hw.ouropencvplatform5/ccm_accel Log files: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/logs/ccm_accel Running Dispatch Server on port:37417 INFO: [v++ 60-1548] Creating build summary session with primary output /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel.xo.compile_summary, at Wed Feb 16 10:28:08 2022 INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Feb 16 10:28:08 2022 Running Rule Check Server on port:33649 INFO: [v++ 60-1315] Creating rulecheck session with output '/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/reports/_x.hw.ouropencvplatform5/ccm_accel/v++_compile_ccm_accel_guidance.html', at Wed Feb 16 10:28:09 2022 INFO: [v++ 60-895] Target platform: /home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/ouropencvplatform5.xpfm INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/home/dev/petali/v31_EV_VitisVision/ouropencvplatform5/export/ouropencvplatform5/hw/xilinx_zcu102_base_202020_1.xsa' INFO: [v++ 60-585] Compiling for hardware target INFO: [v++ 60-423] Target device: ouropencvplatform5 INFO: [v++ 60-242] Creating kernel: 'ccm_accel' WARNING: /tools/Xilinx/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.

===>The following messages were generated while performing high-level synthesis for kernel: ccm_accel Log file: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log : INFO: [v++ 204-61] Pipelining loop 'MMIterInLoop1'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'MMIterInLoop1' INFO: [v++ 204-61] Pipelining loop 'MMIterInLoopRow'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'MMIterInLoopRow' INFO: [v++ 204-61] Pipelining loop 'VITIS_LOOP_136_1'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 1, loop 'VITIS_LOOP_136_1' INFO: [v++ 204-61] Pipelining loop 'colLoop'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 6, loop 'colLoop' INFO: [v++ 204-61] Pipelining loop 'MMIterOutRow_MMIterOutCol'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 2, loop 'MMIterOutRow_MMIterOutCol' INFO: [v++ 204-61] Pipelining loop 'MMIterOutLoop2'. INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'MMIterOutLoop2' INFO: [v++ 200-789] * Estimated Fmax: 205.47 MHz ERROR: [v++ 213-28] Failed to generate IP. ERROR: [v++ 60-300] Failed to build kernel(ip) ccm_accel, see log for details: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log ERROR: [v++ 60-773] In '/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log', caught Tcl error: ERROR: [IMPL 213-28] Failed to generate IP. ERROR: [v++ 60-599] Kernel compilation failed to complete ERROR: [v++ 60-592] Failed to finish compilation INFO: [v++ 60-1653] Closing dispatch client. Makefile:226: recipe for target '_x_temp.hw.ouropencvplatform5/ccm_accel.xo' failed make: [_x_temp.hw.ouropencvplatform5/ccm_accel.xo] Error 1 dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ Makefile.txt

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

I see overall 3 issues in your build:

OpenCV includes error : This is resolved after you added the flags
CL/cl2.hpp not found : Please make sure you have setup the OpenCL environment. If the file is still missing after setup, you can get if from Khronos page here
Failed to generate IP after Synthesis phase : Please post the log (/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log) here.

kapoor7997 commented 2 years ago

vitis_hls.log Hi vt-lib-support,

First of I all I want to provide info about my system.

I have Vivado, Vitis and Petalinux 2020.2 installed on my ubuntu pc.
I am using trial version of Xilinx Software and the trial of Vivado and Vitis. My trial has Expired. But because I am not creating my own xsa, petalinux should still work for me. Thats what I am assuming.
I created the sysroot from my own petalinux project that I created from the xsa file provided by xilinx in their Xilinx base image for ZCU102. Does not having a trial license causes petalinux to fail building.? We are a startup and are looking to do image processing demo to get funding for our project. So we have not bought licence for Vivado/Vitis. But we do have three ZCU102 boards purchased from Xilinx for our Demo.

Now results of your previous instructions: Answer for step2: I followed the step2 of setting up the opencl environment. But I still got the same error. Answer for step3: Attached is the vitis log.

Thanks, Kapoor7997

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

Regarding the effect of license expiration, you can get support on the Xilinx forums.

On the build issues:

This is Vitis environment setup issue. Installing these packages (please choose according to your OS) as mentioned in the Vitis documentation page, should install the required OpenCL headers as claimed in the package details page. If it still doesn't install for you, you may need to get the files and manually copy them to your /usr/include/CL directory.
From your vits_hls.log it is clear that the error is due to y2k22 bug (This AR covers full info on that). You need patch your Vivado/Vitis installation as explained here to overcome it.

kapoor7997 commented 2 years ago

Hi vt-lib-support,

I followed your steps.

I did the patch as you suggested.
I found that my sysroot did not have CL contents. So instead of copying it I used the sysroots provided by xilinx to test this. I also used the xpfm privided by xilinx base image. I also used the EDGE_COMMON_SW from xilinx Common Image of ZCU102.

I created a new Vitis Vision library from github in folder VLStuff2020.2v2.

The commands I used are as follows: export DEVICE=/Downloads/XilinxVision/VisionLibraryStuff2020.2/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm export SYSROOT=/petali/opencv_build/xilinx-zcu102-2020.2/sysroots/aarch64-xilinx-linux/ export EDGE_COMMON_SW=~/Downloads/XilinxVision/VisionLibraryStuff2020.2/CommonImage2020.2/xilinx-zynqmp-common-v2020.2/ make host xclbin TARGET=hw HOST_ARCH=aarch64

Then the synthesis succedded and after running the command make run TARGET=hw HOST_ARCH=aarch64 I was able to get thr sd_card folder. I copied its contents to the sd card and was able to boot up.

Here we are using Xilinx's sysroots, xilinx common image files and xilinx xsa for platform .xpfm and the console output after running the run_script.sh is:

root@xilinx-zcu102-2020_2:/media/sd-mmcblk0p1# sh run_script.sh INFO: Running OpenCL section. [ 91.326668] [drm] Pid 1107 opened device [ 91.330616] [drm] Pid 1107 closed device Found Platform Platform Name: Xilinx [ 91.341017] [drm] Pid 1107 opened device [ 91.348234] [drm] Pid 1107 closed device [ 91.352218] [drm] Pid 1107 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 92.649003] [drm] get section DEBUG_IP_LAYOUT err: -22 [ 92.649012] [drm] get section AIE_METADATA err: -22 [ 92.654271] [drm] zocl_xclbin_read_axlf 93f614ba-cb98-4705-9a7d-dd2105b76aec ret: 0 [ 92.666065] [drm] bitstream 93f614ba-cb98-4705-9a7d-dd2105b76aec locked, ref=1 [ 92.673747] [drm] No ERT scheduler on MPSoC, using KDS [ 92.686158] [drm] scheduler config ert(0) [ 92.686160] [drm] cus(1) [ 92.690161] [drm] slots(16) [ 92.692857] [drm] num_cu_masks(1) [ 92.695813] [drm] cu_shift(16) [ 92.699291] [drm] cu_base(0x80000000) [ 92.702510] [drm] polling(0) [ 92.706365] [drm] bitstream 93f614ba-cb98-4705-9a7d-dd2105b76aec unlocked, ref=0

Then we found from here(https://support.xilinx.com/s/article/1138667?language=en_US) that we need to add zocl, xrt and other things to the user-rootfsconfig. Now we had to create our own petalinux project because we dont have access to xilinx's petalinux project. So we created our own petalinux project with opencv enabled like its shown here(https://opencvguide.readthedocs.io/en/latest/opencvpetalinux/basics.html), And then added the following to the user-rootfsconfig like this:

CONFIG_xrt CONFIG_xrt-dev CONFIG_zocl CONFIG_opencl-clhpp-dev CONFIG_opencl-headers-dev CONFIG_packagegroup-petalinux-opencv CONFIG_opencv

And then in the rootfs config → Filesystem Packages → libs, we enabled the following: opencv opencl-clhpp opencl-headers xrt zocl

And then added device tree entry to the system-user.dtsi like this:

&axi_intc_0 { xlnx,kind-of-intr = <0x0>; xlnx,num-intr-inputs = <0x20>; };

&amba { zyxclmm_drm { compatible = "xlnx,zocl"; status = "okay"; interrupt-parent = <&axi_intc_0>; interrupts = <0 4>, <1 4>, <2 4>, <3 4>, <4 4>, <5 4>, <6 4>, <7 4>, <8 4>, <9 4>, <10 4>, <11 4>, <12 4>, <13 4>, <14 4>, <15 4>, <16 4>, <17 4>, <18 4>, <19 4>, <20 4>, <21 4>, <22 4>, <23 4>, <24 4>, <25 4>, <26 4>, <27 4>, <28 4>, <29 4>, <30 4>, <31 4>; }; };

and then created our image files from this petalinux project and then used xilinx's sysroots tobuild sd_card files and then ran this on the board after building. And we got the same error

Console output after running run_script.sh with our petalinux project:

root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# sh init.sh . root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# sh run_script.sh INFO: Running OpenCL section. [ 101.746511] [drm] Pid 861 opened device [ 101.750373] [drm] Pid 861 closed device Found Platform Platform Name: Xilinx [ 101.760711] [drm] Pid 861 opened device [ 101.767879] [drm] Pid 861 closed device [ 101.771828] [drm] Pid 861 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 103.076301] [drm] get section DEBUG_IP_LAYOUT err: -22 [ 103.076311] [drm] get section AIE_METADATA err: -22 [ 103.081573] [drm] zocl_xclbin_read_axlf 60b39d9d-aeac-4b30-9f74-2fbe9a56547d ret: 0 [ 103.093465] [drm] bitstream 60b39d9d-aeac-4b30-9f74-2fbe9a56547d locked, ref=1 [ 103.101142] [drm] No ERT scheduler on MPSoC, using KDS [ 103.113558] [drm] scheduler config ert(0) [ 103.113560] [drm] cus(1) [ 103.117569] [drm] slots(16) [ 103.120264] [drm] num_cu_masks(1) [ 103.123223] [drm] cu_shift(16) [ 103.126702] [drm] cu_base(0x80000000) [ 103.129923] [drm] polling(0) [ 103.133776] [drm] bitstream 60b39d9d-aeac-4b30-9f74-2fbe9a56547d unlocked, ref=0

How do we resolve this error. We found from here(https://github.com/Xilinx/XRT/issues/2747) that zocl interrupt is not ariving. Do we need hardware(xsa) changes for this? If yes then, we dont have access to xilinx's vivado project. What do you want in vivado block diagram and vivado settings to build this xsa with zocl. Why is this info not mentioned anywhere not even in the Vitis Vision Readme?

Need Help!!!

Regards, kapoor7997

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

Good to know that you were able to build and generate the sd_card for your project with the base platform.

Before going to the analysis of runtime error, we would like to state that there is no need to update/modify/edit any parts of the generated sd_card image and it is expected to run as is. The article you pointed to is for creating a custom software platform instead of using Xilinx base platform. So it does not apply here.

On the error, it could be an issue with the XRT version. You may try the following; On a new terminal, in the same project folder, source all the environment settings except the xrt and do the host and sd_card build as follows (this forces the executable to use the xrt from sysroot instead of local system):

source /tools/Xilinx/Vitis/2020.2/settings64.sh
export DEVICE = ~/Downloads/XilinxVision/VisionLibraryStuff2020.2/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm
export SYSROOT=~/petali/opencv_build/xilinx-zcu102-2020.2/sysroots/aarch64-xilinx-linux/
export EDGE_COMMON_SW=~/Downloads/XilinxVision/VisionLibraryStuff2020.2/CommonImage2020.2/xilinx-zynqmp-common-v2020.2/
make host sd_card TARGET=hw HOST_ARCH=aarch64

kapoor7997 commented 2 years ago

Hi vt-lib-support,

I used all xilinx files and ran exact commands given by you. And as you suggested, I didn't source the xrt source /tools/Xilinx/Vitis/2020.2/settings64.sh export DEVICE = /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm export SYSROOT=home/dev/petali/opencv_build/xilinx-zcu102-2020.2/sysroots/aarch64-xilinx-linux/ export EDGE_COMMON_SW=/home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/CommonImage2020.2/xilinx-zynqmp-common-v2020.2/

make host sd_card TARGET=hw HOST_ARCH=aarch64

And this is the result of the device console after executing the script run_script.sh

root@zynqmp-common-2020_2:~# root@zynqmp-common-2020_2:~# cd /mnt/sd-mmcblk0p1/ root@zynqmp-common-2020_2:/mnt/sd-mmcblk0p1# ls 128x128.png BOOT.BIN boot.scr emconfig.json krnl_ccm.xclbin run_script.sh 4k.jpg Image ccm init.sh platform_desc.txt system.dtb root@zynqmp-common-2020_2:/mnt/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ root@zynqmp-common-2020_2:/mnt/sd-mmcblk0p1# sh run_script.sh INFO: Running OpenCL section. [ 76.764173] [drm] Pid 1338 opened device [ 76.768120] [drm] Pid 1338 closed device Found Platform Platform Name: Xilinx [ 76.778510] [drm] Pid 1338 opened device [ 76.785751] [drm] Pid 1338 closed device [ 76.789781] [drm] Pid 1338 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 78.096153] [drm] get section DEBUG_IP_LAYOUT err: -22 [ 78.096161] [drm] get section AIE_METADATA err: -22 [ 78.101416] [drm] zocl_xclbin_read_axlf caf49ea2-bc8c-43fb-b2c5-f716414c1f19 ret: 0 [ 78.113205] [drm] bitstream caf49ea2-bc8c-43fb-b2c5-f716414c1f19 locked, ref=1 [ 78.120886] [drm] No ERT scheduler on MPSoC, using KDS [ 78.133280] [drm] scheduler config ert(0) [ 78.133281] [drm] cus(1) [ 78.137285] [drm] slots(16) [ 78.139976] [drm] num_cu_masks(1) [ 78.142934] [drm] cu_shift(16) [ 78.146417] [drm] cu_base(0x80000000) [ 78.149635] [drm] polling(0) [ 78.153490] [drm] bitstream caf49ea2-bc8c-43fb-b2c5-f716414c1f19 unlocked, ref=0

Attached is the picture of the xrt version from my board after building sd_card folder XRTVersionFromBoardXilinxAllFiles

I have also attached the contents of the XRT library folder from the sysroots provided by xilinx which I used for building XRT_libraryFilesInSysroots

THEN I used the "make host xclbin TARGET=hw HOST_ARCH=aarch64" and "make run TARGET=hw HOST_ARCH=aarch64" and the console output is the following

I ran run_script twice and console output is the following

1st run root@zynqmp-common-2020_2:~# cd /media/sd-mmcblk0p1/ root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# ls 128x128.png BOOT.BIN boot.scr emconfig.json krnl_ccm.xclbin run_script.sh 4k.jpg Image ccm init.sh platform_desc.txt system.dtb root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh init.sh . root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh init.sh . root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh run_script.sh INFO: Running OpenCL section. [ 147.920320] [drm] Pid 1525 opened device [ 147.924267] [drm] Pid 1525 closed device Found Platform Platform Name: Xilinx [ 147.932432] [drm] Pid 1525 opened device [ 147.939683] [drm] Pid 1525 closed device [ 147.943670] [drm] Pid 1525 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 149.248325] [drm] get section DEBUG_IP_LAYOUT err: -22 [ 149.248333] [drm] get section AIE_METADATA err: -22 [ 149.253589] [drm] zocl_xclbin_read_axlf 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 ret: 0 [ 149.265378] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 locked, ref=1 [ 149.273057] [drm] No ERT scheduler on MPSoC, using KDS [ 149.285455] [drm] scheduler config ert(0) [ 149.285457] [drm] cus(1) [ 149.289457] [drm] slots(16) [ 149.292160] [drm] num_cu_masks(1) [ 149.295124] [drm] cu_shift(16) [ 149.298602] [drm] cu_base(0x80000000) [ 149.301823] [drm] polling(0) [ 149.305676] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 unlocked, ref=0 ^C[ 149.311266] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 locked, ref=1 Here I pressed ctrl+c to shut it down [ 502.074613] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 502.600904] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 503.112920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 503.624920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 504.136920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 504.648906] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 505.160920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 505.672893] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 506.184893] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 506.696898] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 507.208920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 507.720920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 508.232894] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 508.744904] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 509.256894] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 509.768920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 510.280920] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 510.792903] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 511.304921] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 511.817034] [drm] pid(1525) waiting for outstanding 1 cmds to finish [ 512.328909] [drm:zocl_client_release [zocl]] ERROR Please investigate stale cmds [ 512.342817] [drm] addr 0x80000000, status 0x1 [ 512.342822] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 unlocked, ref=0 [ 512.347174] [drm] Pid 1525 closed device

2nd run root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh init.sh . root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh run_script.sh INFO: Running OpenCL section. [ 541.211499] [drm] Pid 2545 opened device [ 541.215438] [drm] Pid 2545 closed device Found Platform Platform Name: Xilinx [ 541.220087] [drm] Pid 2545 opened device [ 541.227347] [drm] Pid 2545 closed device [ 541.231403] [drm] Pid 2545 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 541.424158] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded [ 541.424174] [drm] zocl_xclbin_read_axlf 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 ret: 0 [ 541.437093] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 locked, ref=1 [ 541.444770] [drm] Reconfiguration not supported [ 541.456544] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 unlocked, ref=0

root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh init.sh . root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# sh run_script.sh INFO: Running OpenCL section. [ 541.211499] [drm] Pid 2545 opened device [ 541.215438] [drm] Pid 2545 closed device Found Platform Platform Name: Xilinx [ 541.220087] [drm] Pid 2545 opened device [ 541.227347] [drm] Pid 2545 closed device [ 541.231403] [drm] Pid 2545 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 541.424158] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded [ 541.424174] [drm] zocl_xclbin_read_axlf 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 ret: 0 [ 541.437093] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 locked, ref=1 [ 541.444770] [drm] Reconfiguration not supported [ 541.456544] [drm] bitstream 8c79d16e-6eeb-4c0f-adb8-4bc2a49dc217 unlocked, ref=0

Also Attached the complete colsole output from the run. ErrorWithXilinx_Files.txt

Thanks, Kapoor7997

kapoor7997 commented 2 years ago

My setup includes: -ubuntu 18.04.4 -vivado 2020.2 and vitis 2020.2 -petalinux 2020.2 -XRT installed at /opt/xilinx/xrt (Please guide me on which XRT version is the compatible version of XRT for this as you were concerned about the xrt version)

I built everything from scratch cause I wanted to be sure non of my changes affect the build. So I downloaded:-

Fresh copy of Xilinx common image (xilinx-zynqmp-common-v2020.2)
Freshly created a sysroots from xilinx common image by running the sdk.sh script
Fresh copy zcu102 base platform

COMMANDS: I used the following commands for setting the environment variables for the colorcorrectionmatrix example from L2:-

source /tools/Xilinx/Vitis/2020.2/settings64.sh export DEVICE=/home/dev/Downloads/XilinxVision/newtry/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm export SYSROOT=/home/dev/Downloads/XilinxVision/newtry/xilinx-zynqmp-common-v2020.2/sysroots/sysroots/aarch64-xilinx-linux/ export EDGE_COMMON_SW=/home/dev/Downloads/XilinxVision/newtry/xilinx-zynqmp-common-v2020.2/ make host sd_card TARGET=hw HOST_ARCH=aarch64

Note: I did not add any of the following additional flags CXXFLAGS += -I$(SYSROOT)/usr/include CXXFLAGS += --sysroot=$(SYSROOT) LDFLAGS += -L$(SYSROOT)/usr/lib LDFLAGS += -L${SYSROOT}/opt/xilinx/xrt/lib as you suggested before because I am using xilinx base image platform, common image and sysroots and I am not using my custom hardware

Here is the console output in a text file for the run on hardware(zcu102 board) newtry_SameError.txt

The output looks like this root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# export XCL_BINDIR=/media/sd-mmcblk0p1 root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# ./run_script.sh INFO: Running OpenCL section. [ 103.501693] [drm] Pid 1203 opened device [ 103.505637] [drm] Pid 1203 closed device Found Platform Platform Name: Xilinx [ 103.513852] [drm] Pid 1203 opened device [ 103.521079] [drm] Pid 1203 closed device [ 103.525117] [drm] Pid 1203 opened device INFO: Device found - xilinx_zcu102_base_202020_1 XCLBIN File Name: krnl_ccm INFO: Importing ./krnl_ccm.xclbin Loading: './krnl_ccm.xclbin' [ 104.822674] [drm] get section DEBUG_IP_LAYOUT err: -22 [ 104.822682] [drm] get section AIE_METADATA err: -22 [ 104.827934] [drm] zocl_xclbin_read_axlf 31492852-c64f-4e1b-bce6-787d18e94202 ret: 0 [ 104.839754] [drm] bitstream 31492852-c64f-4e1b-bce6-787d18e94202 locked, ref=1 [ 104.847428] [drm] No ERT scheduler on MPSoC, using KDS [ 104.859827] [drm] scheduler config ert(0) [ 104.859829] [drm] cus(1) [ 104.863829] [drm] slots(16) [ 104.866527] [drm] num_cu_masks(1) [ 104.869486] [drm] cu_shift(16) [ 104.872970] [drm] cu_base(0x80000000) [ 104.876183] [drm] polling(0) [ 104.880068] [drm] bitstream 31492852-c64f-4e1b-bce6-787d18e94202 unlocked, ref=0

QUESTION Ques1: Does the base image platform have zocl and interrupts setup correectly in vivado design/hardware file(xsa). Ques2: Do we need hardware changed that the base image xsa doesnt have? As suggested by this thread https://github.com/Xilinx/XRT/issues/2747 Ques3: If we do need hardware changes, what changes do we need?

Thanks, kapoor7997

vt-lib-support commented 2 years ago

Hi @kapoor7997 ,

Ques1: Does the base image platform have zocl and interrupts setup correectly in vivado design/hardware file(xsa). Ans : Yes Ques2: Do we need hardware changed that the base image xsa doesnt have? As suggested by this thread https://github.com/Xilinx/XRT/issues/2747 Ans: No Ques3: If we do need hardware changes, what changes do we need? Ans: No need of any changes

This looks like some issue with the hardware setup and not with the library code. (Please run software emulation and hardware emulation to confirm on your end too)

We suggest you to create a ticket in the Xilinx forums where you can get the technical assistance to debug your stall issue on the board. This page has the info on the process.

kapoor7997 commented 2 years ago

Hi vt-lib-support,

As per your suggestion, we tried hw_emu and sw_emu. we ran the following commands from this link(https://xilinx.github.io/Vitis_Libraries/vision/2020.1/overview.html section Evaluating the Functionality)

source /tools/Xilinx/Vitis/2020.2/settings64.sh source /opt/xilinx/xrt/setup.sh export DEVICE=/home/dev/Downloads/XilinxVision/newtry/xilinx_zcu102_base_202020_1/xilinx_zcu102_base_202020_1.xpfm export SYSROOT=/home/dev/Downloads/XilinxVision/newtry/xilinx-zynqmp-common-v2020.2/sysroots/sysroots/aarch64-xilinx-linux/ make host xclbin TARGET=hw_emu BOARD=Zynq ARCH=aarch64

And

make host xclbin TARGET=sw_emu BOARD=Zynq ARCH=aarch64

In both cases we used xilinx base image and xilinx common image for sysroot. Looks like the same erorrs on both cases.

We got multiple errors and logs are attached. hw_emu_errors.txt sw_emu_errors.txt

We have been working on getting the vitis vision libraries working for a month now and haven't gotten anywhere. 10 days ago, the vt-lib-support team completely stopped replying. We are loosing confidence in xilinx and xilinx products at this point. We are in the process of a multi-million dollar deal and we built our custom hardware using and following the zcu102 board. We have invested more than a million dollars in developing hardware with xilinx FPGA(9 FPGA's per board) and at this point all the xilinx base images, base software and base hw has failed to provide us with a working demo of the simplest functionality. We would really appreciate some concrete help in this process.

I represent Crypto-knight Mining Corp from Vancouver.

Thanks, kapoor7997

Xilinx / Vitis_Libraries

Can't build a simple vision/L2 example #80