It seems like the main/currently recommended way to program the XCLBIN file is to do device.load_xclbin(binaryFile) (where device is xrt::device(idx)) in the C++ host/driver code. This is seen in the following example code (given by Xilinx):
I was wondering if I could instead load the XCLBIN beforehand using xbutil program -d BDF -u XCLBIN and then modify the line that does load_xclbin in the driver to device.get_xclbin_uuid() (I think this should work since the downstream xrt::kernel(device, uuid, "vvadd") call needs just the UUID).
I try this in the following fork of Vitis_Accel_Examples:
terminate called after throwing an instance of 'xrt_core::error'
what(): xclbin id mismatch: Invalid argument
I have verified that the UUID given by the get_xclbin_uuid function returns the exact same string as when I check the UUID in xclbinutil --info --input XCLBIN.
It seems like the main/currently recommended way to program the XCLBIN file is to do
device.load_xclbin(binaryFile)
(wheredevice
isxrt::device(idx)
) in the C++ host/driver code. This is seen in the following example code (given by Xilinx):https://github.com/Xilinx/Vitis_Accel_Examples/blob/53e7d4fd8e1a8a431b53aff47dfcb6c5d19d9686/host_xrt/hello_world_xrt/src/host.cpp#L47-L50
I was wondering if I could instead load the XCLBIN beforehand using
xbutil program -d BDF -u XCLBIN
and then modify the line that doesload_xclbin
in the driver todevice.get_xclbin_uuid()
(I think this should work since the downstreamxrt::kernel(device, uuid, "vvadd")
call needs just the UUID).I try this in the following fork of
Vitis_Accel_Examples
:https://github.com/abejgonzalez/Vitis_Accel_Examples/blob/72ff508c6465d04cf9b8411f3ea8c37f2aa59ff9/host_xrt/hello_world_xrt/src/host.cpp#L47-L52
https://github.com/abejgonzalez/Vitis_Accel_Examples/blob/72ff508c6465d04cf9b8411f3ea8c37f2aa59ff9/host_xrt/hello_world_xrt/Makefile#L167-L169
However, this leads to an error saying:
I have verified that the UUID given by the
get_xclbin_uuid
function returns the exact same string as when I check the UUID inxclbinutil --info --input XCLBIN
.Any recommendations/thoughts on how to solve this issue? Is it even possible to do this two-stage loading. You should be able to reproduce the issue in the fork mentioned (https://github.com/abejgonzalez/Vitis_Accel_Examples/blob/72ff508c6465d04cf9b8411f3ea8c37f2aa59ff9/host_xrt/hello_world_xrt/) if you replace the BDF in the
Makefile
with your specific FPGA BDF. Thanks in advance.