Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
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xvcServer: Add support for Zynq Ultrascale+ MPSOC platform #5
This patch does the below
--> Added barrier after every register write, It just make sure that write
would not be merged into CPU cluster's interior write buffer with previous
data that haven't been write to device.
--> Increased buffer array size.
This patch does the below --> Added barrier after every register write, It just make sure that write would not be merged into CPU cluster's interior write buffer with previous data that haven't been write to device. --> Increased buffer array size.
Signed-off-by: Appana Durga Kedareswara rao appana.durga.rao@xilinx.com