Open maldag opened 5 years ago
html,body{background-color:#fff;color:#333;line-height:1.4;font-family:sans-serif,Arial,Verdana,Trebuchet MS;}Unfortunaly not. I haven't really been focusing on that issue since this project doesn't really seem to get much support by Xilinx. straytms schrieb am 13.04.2020 11:49 (GMT +02:00):
Hi, maldag, did you fixed the problem with your modified code?
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@maldag Apologies for the delay in response. If you still encounter this issue, can you try disabling CPU IDLE in kernel config as discussed here - https://support.xilinx.com/s/question/0D52E00006hpgSpSAI/petalinux-on-ultrascale-freezes-when-loaded-via-xvc-jtag-interface?language=en_US ?
I'm also looking at integrating XVC into a yocto based project. Did this issue ever get resolved @maldag? (maybe you have published a yocto .bb-file/recipe for XVC?)
Haven't done it yet. Since we're not up to date with the latest kernel and such, we haven't had a chance to get back to it. So if you fix it, please let me know @andrsmllr
I'm using 2023.1 and running into the same issue with a very similar set up. CPU idle is disabled.
Here the same as well. I am using 2021.2 with CPU idle disabled and still the system freezes after XVC is running for some time.
This makes it barely functional.
My problem ended up being that the debug bridge was not marked debug (IP issue IMO) which caused the entire AXI subsystem it was connected to to be optimized away. You may need to manually mark things as debug to get it from ripping the design away.
If that is the case maybe someone should close this issue.
I think there are several issues here.
I've implemented the xvc server in our custom project using yocto based on petalinux and vivado 2018.2
The server running in userspace works well with the kernel driver using IOCTL with the vivado hardware manager in version 2018.2
After starting my custom made application the whole linux system freezes, if I try to connect to the xvc server from Vivado hardware manager.
System is a zynq7000 board, linux kernel 4.14, debug_bridge_0 connected at 0x8000000 (AXI_1) which is the only participant on this AXI peripheral. My custom fpga ip-cores are all mapped to AXI_0 or ACP.
Is there any synchronization mechanism required in the kernel to secure access to the AXI peripheral?
I needed to patch some parts of your code to avoid the TCP SYN error ...