Xilinx / blockchainacceleration

https://xilinx.github.io/blockchainacceleration/
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Failed to build #5

Open stonux opened 2 years ago

stonux commented 2 years ago

Hi,

I tried ti build this project on

Linux 5.4.0-91-generic #102-Ubuntu SMP Fri Nov 5 16:31:28 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux

xilinx-u55n-gen3x4-xdma-1-202110-1-dev-1-3236984.noarch.rpm

  | *** Running vivado
  | with args -log level0_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source level0_wrapper.tcl -notrace
  |  
  |  
  | ****** Vivado v2021.2 (64-bit)
  | **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  | **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
  | ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 

It issued the following errors:

Starting Connectivity Check Task
--
  |  
  | Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 17348.559 ; gain = 0.000 ; free physical = 92315 ; free virtual = 111167
  | Ending Logic Optimization Task \| Checksum: 2bde5cfe2
  |  
  | Time (s): cpu = 00:06:46 ; elapsed = 00:04:35 . Memory (MB): peak = 17348.559 ; gain = 0.000 ; free physical = 92314 ; free virtual = 111166
  |  
  | Starting Netlist Obfuscation Task
  | Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 17348.559 ; gain = 0.000 ; free physical = 92313 ; free virtual = 111165
  | Ending Netlist Obfuscation Task \| Checksum: 2bde5cfe2
  |  
  | Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 17348.559 ; gain = 0.000 ; free physical = 92313 ; free virtual = 111165
  | INFO: [Common 17-83] Releasing license: Implementation
  | 372 Infos, 243 Warnings, 4 Critical Warnings and 0 Errors encountered.
  | opt_design completed successfully
  | opt_design: Time (s): cpu = 00:07:28 ; elapsed = 00:05:04 . Memory (MB): peak = 17348.559 ; gain = 32.016 ; free physical = 92338 ; free virtual = 111190
  | WARNING: [Vivado 12-180] No cells matched 'level0_i/ulp/ethash_kernel0/inst/s0ping_V_U/ethash_kernel0_mixdag_s0ping_V_ram_U/ram_reg_uram_0'.
  | ERROR: [VPL_TCL 101-2] ERROR: [Common 17-55] 'set_property' expects at least one object.
  | Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  | ERROR: [VPL_TCL 101-3] sourcing script /home/beat/git/blockchainacceleration/hw/ethash8Greturn/build_dir.hw.u55n_gen3x4/link/vivado/vpl/scripts/impl_1/_full_place_pre.tcl failed
  | INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 22:52:15 2021...

On which platform and software versions is this project known to build correctly?

stonux commented 2 years ago

https://support.xilinx.com/s/question/0D52E00006qbi9fSAA/compiling-the-varium-c1100-kernel-fails?language=en_US other versions fail as well.

vt-lib-support commented 2 years ago

Hi @stonux , According to https://pages.gitenterprise.xilinx.com/FaaSApps/EthereumMiner/system_req.html, this solution is build with Vitis 2021.1. The later 2021.2 might have difference in connectivity check.

developeralgo8888 commented 2 years ago

@vt-lib-support , The ethash kernel build fails with any version of Vitis 2021.1 or Vitis 2021.2 . Both fail. so i am not sure where they are getting that idea from. You are the support guy, should you be trying to fix this ??

stonux commented 2 years ago

Hi @stonux , According to https://pages.gitenterprise.xilinx.com/FaaSApps/EthereumMiner/system_req.html, this solution is build with Vitis 2021.1. The later 2021.2 might have difference in connectivity check.

Server not found. Please update your links. There are a lot of broken links in the Xilinx documentation since github somehow changed the URL scheme (offloading from the host name to the path). It would be worth investing into a link bot that also checks the links in PDF documents.

chunsj commented 2 years ago

To me, it seems that the main source of this error lies in the fact that the cell naming convention has been changed since pre_place.tcl file was written (and maybe Vitis version also has been changed).

My question is that should this pre_place thing be done? Without these cell replacement script, the kernel could be successfully built (at least to me) with Vitis 2021.2.

Almost no response from Xilinx since last year, so I do not know if my assertion is correct of not.