Xilinx / dma_ip_drivers

Xilinx QDMA IP Drivers
https://xilinx.github.io/dma_ip_drivers/
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what is the unit of xdma BW in xdma run test #266

Open zjb2023 opened 8 months ago

zjb2023 commented 8 months ago

Info: Number of enabled h2c channels = 1 Info: Number of enabled c2h channels = 1 Info: The PCIe DMA core is memory mapped. Info: Running PCIe DMA memory mapped write read test transfer size: 1024, count: 1 Info: Writing to h2c channel 0 at address offset 0. Info: Wait for current transactions to complete. /dev/xdma0_h2c_0 Average BW = 1024, 5.135870 Info: Writing to h2c channel 0 at address offset 1024. Info: Wait for current transactions to complete. /dev/xdma0_h2c_0 Average BW = 1024, 7.261176 Info: Writing to h2c channel 0 at address offset 2048. Info: Wait for current transactions to complete.

BW=1024 , 7.261176 does it mean 7.26GBps?