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Xilinx / dma_ip_drivers

Xilinx QDMA IP Drivers
https://xilinx.github.io/dma_ip_drivers/
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xdma: read write fpga user reg abnormal #278

Open gongshuaiqi opened 2 months ago

gongshuaiqi commented 2 months ago

I have a problem

CPU and FPGA，PCIE x1

I read and write the FPGA user space reg in the following order： write read write，

but the order of the FPGA capture is read write write

I disassembled the CPU code，the order is write read write, ok

why Read/write sequence error ？

thank you very much

hinxx commented 2 months ago

I'm guessing this is from your code and not using reg_rw utility from this repo or similar.

Are doing read()/write() syscalls or mmap()?

FWIW, mmap() always does the right thing for me (did not try read()/write() myself).