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Xilinx Embedded Software (embeddedsw) Development
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uartps interrupt is not working #286

Open Ryaninthegame opened 8 months ago

Ryaninthegame commented 8 months ago

My board is the Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit, and I need to port the UARTPS driver to run on the PMU. When I execute xuartps_intr_example.c, it hangs within the while loop at line 285. I suspect that the UART interrupt handler is not working.

My UART0 is used for printing logs, and UART1 is used for transmitting data.

The following are my configurations. I have no idea where the problem is. I would appreciate it if someone could help me resolve it. Thank you.

#define INTC                                XIntc
#define INTC_DEVICE_ID      1
#define UART_INT_IRQ_ID     54
XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = {
    {
        (u16)XPAR_XUARTPS_0_DEVICE_ID,           // 0
        (u32)XPAR_XUARTPS_0_BASEADDR,            // 0xFF000000
        (u32)XPAR_XUARTPS_0_UART_CLK_FREQ_HZ,    // 99990005
        (s32)0
    },
    {
        (u16)XPAR_XUARTPS_1_DEVICE_ID,           // 1
        (u32)XPAR_XUARTPS_1_BASEADDR,            // 0xFF010000
        (u32)XPAR_XUARTPS_1_UART_CLK_FREQ_HZ,    // 99990005
        (s32)0
    }
};  
#define XPAR_XINTC_NUM_INSTANCES      2          /* Number of instances */

#define XPAR_INTC_0_DEVICE_ID         1          /* Device ID for instance */
#define XPAR_INTC_0_BASEADDR          0x70800000 /* Register base address */
#define XPAR_INTC_0_ACK_BEFORE        0xFFFF00FF /* Ack timing, before/after */

#define XPAR_INTC_1_DEVICE_ID         2          /* Device ID for instance */
#define XPAR_INTC_1_BASEADDR          0x70800020 /* Register base address */
#define XPAR_INTC_1_ACK_BEFORE        0xFFFF00FF /* Ack timing, before/after */

XIntc_Config XIntc_ConfigTable[XPAR_XINTC_NUM_INSTANCES] = {
    {
        XPAR_INTC_0_DEVICE_ID,  /* Unique ID  of device */
        XPAR_INTC_0_BASEADDR,   /* Register base address */      
        XPAR_INTC_0_ACK_BEFORE, /* Ack before or after service */
        0                       /* Device options */
     }
    ,
    {
        XPAR_INTC_1_DEVICE_ID,  /* Unique ID  of device */
        XPAR_INTC_1_BASEADDR,   /* Register base address */
        XPAR_INTC_1_ACK_BEFORE, /* Ack before or after service */
        0                       /* Device options */
     }
};
gsrinivasgoud commented 7 months ago

@Ryaninthegame For PMU interrupt will be routed through iomodule(Dedicated Hard interrupt controller) and not through AXI INTC, external interrupts can't be connected to the iomodule. my I know interrupt controller output connection in your design?