PMUFW: Missing pin group for QSPI in single mode

Xilinx / embeddedsw

Xilinx Embedded Software (embeddedsw) Development

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Open andreamerello opened 4 years ago

andreamerello commented 4 years ago

Depending by the QSPI mode, a reduced pin set is used by the controller. (e.g. "single" qspi mode -> MIO0 to MIO5).

The PMU firmware, however, doesn't provide such reduced pin-groups for the QSPI function.

CarstenHansenHBK commented 3 years ago

For anyone else running into this issue, we ended up patching the ARM Trusted Firmware - see https://github.com/Xilinx/arm-trusted-firmware/pull/3.