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Xilinx / finn-base

Open Source Compiler Framework using ONNX as Frontend and IR
https://finn-base.readthedocs.io/
BSD 3-Clause "New" or "Revised" License
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Verilator: force inlining, disable common warnings #33

Closed fpjentzsch closed 3 years ago

fpjentzsch commented 3 years ago
  1. In some cases Verilator will not inline all FIFOs, hindering the current method for reading internal signals, which is required for the simulation-based automatic FIFO sizing in InsertAndSetFIFODepths(). Solved by forcing inlining with --inline-mult 0 for now.
  2. Disabled some of the most common warnings by default.

Depends on a pyverilator PR: https://github.com/maltanar/pyverilator/pull/3

To do: adjust finn commit pointers to finn-base & pyverilator accordingly.