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Xilinx / finn-base

Open Source Compiler Framework using ONNX as Frontend and IR
https://finn-base.readthedocs.io/
BSD 3-Clause "New" or "Revised" License
29 stars 17 forks source link

rtlsim improvements #47

Closed maltanar closed 3 years ago

maltanar commented 3 years ago

Changes and fixes to components using pyverilator rtlsim to allow multiple graph inputs/outputs, and allowing extra custom args to be passed to pyverilator for stitched-IP rtlsim.