RTL SWG CPPsim - Githubissues

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

681 stars 218 forks source link

RTL SWG CPPsim #1014

Closed mmrahorovic closed 3 months ago

mmrahorovic commented 3 months ago

Interleave output of RTL-SWG in CPPsim (according to SIMD) such that following VVAU (which is assumed to be VVAU_hls, VVAU_rtl or VVAU and not a MatMul node) executes the matrix multiplication correctly given it's PE parallelism.