Bug fix for FIFO count range mismatch between Python and RTL

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Bug fix for FIFO count range mismatch between Python and RTL #1044

Closed auphelia closed 2 months ago

auphelia commented 2 months ago

This PR introduces a new parameter in the RTL implementation of the StreamingFIFO component which propagates the count width value from the code generation in Python to the verilog component. Bug fix for https://github.com/Xilinx/finn/issues/998.