For larger networks, the time of the blockdesign generation increases significantly, because Vivado reparses all verilog files for every added block/module.
The RTL code is packed as an additional step in code_generation_ipgen after generate_hdl. The PrepareIP transformation would take longer, therefore, it is now derived from NodeLocalTransformation to process all nodes in parallel.
For larger networks, the time of the blockdesign generation increases significantly, because Vivado reparses all verilog files for every added block/module.
The RTL code is packed as an additional step in
code_generation_ipgenaftergenerate_hdl. ThePrepareIPtransformation would take longer, therefore, it is now derived fromNodeLocalTransformationto process all nodes in parallel.