Bitstream generation error on notebook : 4_advanced_builder_settings.ipynb

kalahel commented 3 weeks ago

Quick summary

When trying to run the complete version (last line uncommented) of the notebook notebooks/advanced/4_advanced_builder_settings.ipynb I have an error on step 19 - Synthesis of the bitfile.

Details

Setup

My setup is a WSL2 running ubuntu with Vivado 2024.1 using the main branch of Finn.

Steps to Reproduce

Clone the FINN repository with commit hash: 9d29968
Run export FINN_XILINX_PATH=/home/mathieu/Tools/Xilinx
Run export FINN_XILINX_VERSION=2024.1
Modify the notebook notebooks/advanced/4_advanced_builder_settings.ipynb as such :
- Convert the file to a python script
- Remove all the !ls and %%time commands.
- Uncomment the last line : #build.build_dataflow_cfg(model_file, cfg_build);
Start the docker container with the command: ./run-docker.sh
Run python ./notebooks/advanced/4_advanced_builder_settings.py

Expected behavior

The script should go to step 21, generate the bitstream and the pynq driver.

Actual behavior

An error is thrown at step 19 :

Running step: step_out_of_context_synthesis [18/21]
Running step: step_synthesize_bitfile [19/21]
ERROR: [Vivado 12-13638] Failed runs(s) : 'impl_1'
Traceback (most recent call last):
  File "/mnt/c/Dev/finn/src/finn/builder/build_dataflow.py", line 158, in build_dataflow_cfg
    model = transform_step(model, cfg)
  File "/mnt/c/Dev/finn/src/finn/builder/build_dataflow_steps.py", line 796, in step_synthesize_bitfile
    model = model.transform(
  File "/mnt/c/Dev/finn/deps/qonnx/src/qonnx/core/modelwrapper.py", line 140, in transform
    (transformed_model, model_was_changed) = transformation.apply(transformed_model)
  File "/mnt/c/Dev/finn/src/finn/transformation/fpgadataflow/make_zynq_proj.py", line 359, in apply
    model = model.transform(MakeZYNQProject(self.platform, enable_debug=self.enable_debug))
  File "/mnt/c/Dev/finn/deps/qonnx/src/qonnx/core/modelwrapper.py", line 140, in transform
    (transformed_model, model_was_changed) = transformation.apply(transformed_model)
  File "/mnt/c/Dev/finn/src/finn/transformation/fpgadataflow/make_zynq_proj.py", line 270, in apply
    raise Exception(
Exception: Synthesis failed, no bitfile found. Check logs under /tmp/finn_dev_mathhann/vivado_zynq_proj_o0c4z7uy
> /mnt/c/Dev/finn/src/finn/transformation/fpgadataflow/make_zynq_proj.py(270)apply()
-> raise Exception(

This is the full log from vivado

But the errors consists mainly of multiple instance of :

ERROR: [DRC REQP-1962] Cascade RAMB36E1 ADDR15 pin check: The RAMB36E1 cell top_i/StreamingDataflowPartition_1/inst/StreamingDataflowPartition_1_MVAU_hls_5/StreamingDataflowPartition_1_MVAU_hls_5_wstrm/inst/core/mem/blkStage2.Mem_reg_1_0 is cascaded with another RAMB36E1 top_i/StreamingDataflowPartition_1/inst/StreamingDataflowPartition_1_MVAU_hls_5/StreamingDataflowPartition_1_MVAU_hls_5_wstrm/inst/core/mem/blkStage2.Mem_reg_0_0, however the top_i/StreamingDataflowPartition_1/inst/StreamingDataflowPartition_1_MVAU_hls_5/StreamingDataflowPartition_1_MVAU_hls_5_wstrm/inst/core/mem/blkStage2.Mem_reg_1_0/ADDRARDADDR[15] pin is not connected to the same signal or same type of tie-off as the top_i/StreamingDataflowPartition_1/inst/StreamingDataflowPartition_1_MVAU_hls_5/StreamingDataflowPartition_1_MVAU_hls_5_wstrm/inst/core/mem/blkStage2.Mem_reg_0_0/ADDRARDADDR[15] pin of the other RAMB.

fpjentzsch commented 3 weeks ago

Hi,

I don't think these notebooks were tested with 2024.1 yet. Maybe this error does not occur with Vivado 2022.2?

kalahel commented 1 week ago

Hi,

You were right, it was link to the version, it works with 2022.2 !

Thanks for the guidance.

Xilinx / finn