Refuse useless clock pumping for SIMD=1. - Githubissues

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Refuse useless clock pumping for SIMD=1. #1232

Open preusser opened 5 days ago