Have IPI recompute AXI-lite address width according to user-defined memory layout.

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Closed preusser closed 1 year ago

preusser commented 1 year ago

Quick fix of IP packaging of memstream for correct address width computation in IPI.