Fix: clean up MinimizeAccumulatorWidth logic for MVAU and VVAU

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Closed i-colbert closed 1 year ago

i-colbert commented 1 year ago

[x] Simplify the minimize_accumulator_width logic
[x] Enable rounding up to nearest 8 exclusively if MVAU/VVAU has no activation and is last node in the graph