Set axilite address range to a minimum of 4K

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Closed auphelia closed 1 year ago

auphelia commented 1 year ago

Vivado IPI requires a minimum of a 4K address range for slaves
This PR adds a tcl command to ensure that the address range is minimum 4K for AXI-lite interface ports during IP stitching