Hotfix: verilator_fifosim for RTL SWG component

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Closed fpjentzsch closed 1 year ago

fpjentzsch commented 1 year ago

The new "swg_pkg" source was correctly added to pyverilate_stitched_ip but not verilator_fifosim.