[Build] Add support for Vivado implementation strategy v++ option

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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[Build] Add support for Vivado implementation strategy v++ option #909

Open jmonks-amd opened 11 months ago

jmonks-amd commented 11 months ago

There are different implementation strategies available in Vivado for routing and closing timing. https://jira.xilinx.com/browse/CR-1171874 brought the relevant v++ option to light. This PR adds support for passing the implementation strategy down to v++.