Xilinx / finn

Dataflow compiler for QNN inference on FPGAs
https://xilinx.github.io/finn
BSD 3-Clause "New" or "Revised" License
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DWC RTL variant #925

Closed auphelia closed 10 months ago

auphelia commented 10 months ago

This PR implements an RTL variant of the datawidth converter. The RTL component will be inserted by default from the transformation InsertDWC, unless the ratio of the input and output streams is not integer then the HLS component will be used.

Please be aware that when this PR is merged, every project that works with the builder will insert automatically RTL DWC if possible.