Error while generating stitched IP

[pkdeep]

Discussed in https://github.com/Xilinx/finn/discussions/926

^{Originally posted by **pkdeep** November 28, 2023} Hello, I am trying to generate FPGA design for my custom DNN. I am getting the some error while running the**"build.build_dataflow_cfg(model_file, cfg_stitched_ip)"** step. ERROR>>>>>>>>>>>>>>>>>>> _**Traceback (most recent call last): File "/opt/conda/lib/python3.8/distutils/file_util.py", line 41, in _copy_file_contents fdst = open(dst, 'wb') FileNotFoundError: [Errno 2] No such file or directory: 'output_ipstitch_ooc_rtlsim/stitched_ip/all_verilog_srcs.txt' During handling of the above exception, another exception occurred: Traceback (most recent call last): File "/home/pradeep/Desktop/finn-brevitas/finn/src/finn/builder/build_dataflow.py", line 168, in build_dataflow_cfg model = transform_step(model, cfg) File "/home/pradeep/Desktop/finn-brevitas/finn/src/finn/builder/build_dataflow_steps.py", line 619, in step_create_stitched_ip copy_tree(model.get_metadata_prop("vivado_stitch_proj"), stitched_ip_dir) File "/opt/conda/lib/python3.8/distutils/dir_util.py", line 161, in copy_tree copy_file(src_name, dst_name, preserve_mode, File "/opt/conda/lib/python3.8/distutils/file_util.py", line 151, in copy_file _copy_file_contents(src, dst) File "/opt/conda/lib/python3.8/distutils/file_util.py", line 43, in _copy_file_contents raise DistutilsFileError( distutils.errors.DistutilsFileError: could not create 'output_ipstitch_ooc_rtlsim/stitched_ip/all_verilog_srcs.txt': No such file or directory**_ >>>>>>>>>>>>>>>>>>>>> I am using Ubuntu Virtual Box (Ubuntu 20.04, Xilinx tools version: 2022.2) on a windows machine. I am attaching the screenshot of the error. 

[auphelia]

Closing this issue because duplicate of answered GitHub discussion: https://github.com/Xilinx/finn/discussions/926