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Xilinx
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finn
Dataflow compiler for QNN inference on FPGAs
https://xilinx.github.io/finn
BSD 3-Clause "New" or "Revised" License
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Add high-level support for communication through ACCL
#931
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cantbeblank24
opened
7 months ago
cantbeblank24
commented
7 months ago
Adds ACCLOut and ACCLIn nodes which send data across FPGAs by invoking ACCL
Currently only point to point communication is supported, but other types of communication might be added
Supports verification with cppsim using ACCLs BFM emulator
I planned two follow-up PRs
Integrate finn-experimental partitioning and extending the build flow to support distributed designs
Adding low-level support for synthesizing designs with ACCL (in conjunction with the work being done on integrating FINN with Coyote)