This PR is now the first one that should be merged.
This PR allows circumventing the limited address space offered by Coyote for the AXILite. An HLS bridge is added between the AXILite control interface from Coyote and the FINN AXILite signals (tlast marker + writeable weights). By configuring the two registers of the HLS bridge (address offset + value), it is possible to write to a full 32 bits address space.
This PR also makes it so that axi stream width converters do not need to be instantiated manually. Upon AXI4Stream width mismatch, a converter is instantiated.
The new commits start at: "Generate width converters".
This PR should be merged after https://github.com/Xilinx/finn/pull/930.This PR is now the first one that should be merged.
This PR allows circumventing the limited address space offered by Coyote for the AXILite. An HLS bridge is added between the AXILite control interface from Coyote and the FINN AXILite signals (tlast marker + writeable weights). By configuring the two registers of the HLS bridge (address offset + value), it is possible to write to a full 32 bits address space.
This PR also makes it so that axi stream width converters do not need to be instantiated manually. Upon AXI4Stream width mismatch, a converter is instantiated.
The new commits start at: "Generate width converters".