Enable analysis report of post synthesis resource utilization in json

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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Enable analysis report of post synthesis resource utilization in json #965

Closed iksnagreb closed 2 months ago

iksnagreb commented 5 months ago

This was already implemented, it was just not called from the step_synthesize_bitfile. According to the last synthesis I ran using Vitis/Vivado 2022.2, the DSP48 utilization seems to be reported in row 10 of the XML table, however the hard-coded index was set to 9 before - I have fixed this as well.