StreamingFIFO count width mismatch between Python and RTL

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

https://xilinx.github.io/finn

BSD 3-Clause "New" or "Revised" License

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StreamingFIFO count width mismatch between Python and RTL #998

Closed lecramdev closed 5 months ago

lecramdev commented 6 months ago

During RTL generation in StreamingFIFO, the $COUNT_RANGE$ variable in the template for the is set to "clog2(depth-1)-1" but in Q_srl.v, the count and maxcount signals are set to "clog2(depth)". Verilator only emits a warning but during FIFO estimation with RTL simulation, the maxcount output overflows if the buffer too small. The output is then zero and the FIFO is removed from the graph. This is a problem especially in larger networks with skip connections.

auphelia commented 6 months ago

Hi @lecramdev,

Thanks for making us aware of this! This is indeed a bug; to represent a count within 0 ≤ count ≤ depth, you actually need a counter of width $clog2(depth+1). The range would then be [$clog2(depth+1)-1:0].

We really appreciate contributions from the community, would you like to submit a solution for the bug to the repo? You could create a PR targeting dev, here are the contribution guidelines.

auphelia commented 5 months ago

Resolved by https://github.com/Xilinx/finn/pull/1044