Xilinx / fpga24_routing_contest

Runtime-First FPGA Interchange Routing Contest @ FPGA’24
https://xilinx.github.io/fpga24_routing_contest/
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report_route_status inconsistency in Vivado and "check.log" #24

Closed RipperJ closed 10 months ago

RipperJ commented 10 months ago

Hi. For the default RWRoute flow, when we try to run the "report_route_status" for routed design -- "rosetta_fd", we see the following report in the Tcl console of Vivado, showing 2270 nets with routing errors. image

However, in the generated log "rosetta_fd_rwroute.check.log", it shows 0 routing error. image

Could you please help clarify how this inconsistency happened?

eddieh-xlnx commented 10 months ago

Hi @RipperJ. This is a great question. First, let me assume that you're able to route all 5 benchmarks normally, and "check.log" shows a pass with no routing errors. However, your question is that upon loading rosetta_fd_rwroute.dcp and doing a report_route_status manually you're seeing some routing errors, is that right?

If so, this inconsistency is one unique to this single benchmark out of the 5. What makes this one different is that it originated as a HLS design that's been pushed through Vitis HLS which causes it to contain a number encrypted IP blocks. Designs with encrypted components require a slightly different flow than just loading the *.dcp file. Specifically, as you can see from our GitHub Actions run, when CheckPhysNetlist uses RapidWright to write out the DCP the following message is printed:

==============================================================================
==                   Writing DCP: rosetta_fd_rwroute.dcp                    ==
==============================================================================
     (Build XDEF Header):            (    0.455s)
(Write XDEF Cache (3/3)):            (    0.159s)
(Write XDEF Cache (2/3)):            (    0.290s)
(Write XDEF Cache (1/3)):            (    0.943s)
INFO: Design Checkpoint '/home/runner/work/fpga24_routing_contest/fpga24_routing_contest/rosetta_fd_rwroute.dcp'
      may contain encrypted cells. To correctly load the design into Vivado, 
      please source this Tcl script to open the checkpoint: 

      source rosetta_fd_rwroute_load.tcl

            (Write EDIF):            (    3.506s)
    (Write XDEF Routing):            (    4.156s)
  (Write XDEF Placement):            (    3.414s)
 (Write XDEF Finalizing):            (    0.007s)
            (Write XDEF):            (    9.490s)
       Write EDIF & XDEF:     9.530s
               Write XDC:     0.008s
------------------------------------------------------------------------------
         [No GC] *Total*:     9.538s

Instead of loading the *.dcp, you'll need to open Vivado and do a source *_load.tcl instead which ensures any encrypted IPs are also loaded alongside the DCP.

To add some more colour, these encrypted IPs are a part of the logical netlist. The full physical netlist containing the names and types of all leaf (primitive) cells, their placements and routing are not encrypted and so we're able to route (and place) without any problems.

RipperJ commented 10 months ago

Thank you @eddieh-xlnx ! With the *_load.tcl script, it works fine now.