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Xilinx / fpga24_routing_contest

Runtime-First FPGA Interchange Routing Contest @ FPGA’24
https://xilinx.github.io/fpga24_routing_contest/
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[WirelengthAnalyzer] Add new connectivity rules #40

Closed zakn-amd closed 10 months ago

zakn-amd commented 10 months ago

Add connectivity rules for cells of type:

Also add a new PIP wirelength entry, some small refactors, and documentation updates to reflect above changes.