search

Xilinx / fpga24_routing_contest

Runtime-First FPGA Interchange Routing Contest @ FPGA’24
https://xilinx.github.io/fpga24_routing_contest/
Other
28 stars 10 forks source link

Update RapidWright with many RWRoute optimizations #47

Closed eddieh-xlnx closed 9 months ago

eddieh-xlnx commented 9 months ago

In combination with #45, updates to RapidWright have brought in a number of RWRoute enhancements, namely:

  1. https://github.com/Xilinx/RapidWright/pull/888 to not consider irrelevant sink pins during routing search
  2. https://github.com/Xilinx/RapidWright/pull/893 to prune the set of sink-pin-fanins considered during routing search
  3. https://github.com/Xilinx/RapidWright/pull/895 to add an option to perform LUT pin swapping

From Before 1 to After 2 the total benchmark runtime decreased 45% from 11526 seconds to 6391 seconds.

Optimization 3 -- LUT pin swapping -- is an option disabled by default which After 3 shows a further 18% runtime reduction to 5264 seconds; however, as stated in the linked comment this improvement is not universal across all benchmarks.