Xilinx / fpga24_routing_contest

Runtime-First FPGA Interchange Routing Contest @ FPGA’24
https://xilinx.github.io/fpga24_routing_contest/
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Fix wirelength_analyzer when terminating at a comb cell (e.g. LUT) #50

Closed eddieh-xlnx closed 10 months ago

eddieh-xlnx commented 11 months ago

An example of this occurring is the case when the LUT drives a hierarchical (out of context) port, so it becomes the terminus.

zakn-amd commented 11 months ago

Lines 443 and 445 in the docstring should be updated to replace tuple with list.

Perhaps a warning should be emitted when terminating on a combinatorial cell, since this breaks the invariant "paths terminate on sequential cells". But, given the example above I suppose the invariant might not actually be invariant.