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Xilinx / fpga24_routing_contest

Runtime-First FPGA Interchange Routing Contest @ FPGA’24
https://xilinx.github.io/fpga24_routing_contest/
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[CheckPhysNetlist] Verify placement & static/clock routing unchanged #64

Closed eddieh-xlnx closed 9 months ago

eddieh-xlnx commented 9 months ago

As part of the contest rules, routers are only allowed to modify the inter-site routing (PIPs) of the input Physical Netlist. Verify this is the case by leveraging RapidWright's DesignComparator feature: https://github.com/Xilinx/RapidWright/pull/931.