search

Xilinx / kria-vitis-platforms

Kria Vitis platforms and overlays
Apache License 2.0
84 stars 40 forks source link

how to build defect-detection app from source? #13

Closed TonyHo722 closed 2 years ago

TonyHo722 commented 2 years ago

Hi,

how to build defect-detection app from source?

I used below source and revision.

- petalinux : xilinx-k26-starterkit-v2021.1-final.bsp
- vivado: 2020.2.2
- kv260-vitis: branch = release-2020.2.2_k26  (https://github.com/Xilinx/kv260-vitis）
- device-tree: branch = release-2020.2.2_k26 (https://github.com/Xilinx/device-tree-xlnx)

I also try below combintaion, both failed.

- petalinux : xilinx-k26-starterkit-v2021.1-final.bsp
- vivado: 2021.1
- kv260-vitis: branch = release-2021.1 (https://github.com/Xilinx/kv260-vitis）
- device-tree: branch = release-2021.1 (https://github.com/Xilinx/device-tree-xlnx)

I can build petalinux image with app, please reference this link https://github.com/Xilinx/kv260-firmware/issues/2#issuecomment-1058819012 but i found the dmesg with error when use the New FPGA Firmware(app) I build.

[   41.405160] xilinx-csi2rxss 80030000.mipi_csi2_rx_subsystem: missing xlnx,csi-pxl-format property

I think this issue is caused by the .dtsi file - tool auto generated.

xlnx,csi-pxl-format = "YUV422_8bit"; => this setting cause the error in .dtsi file

My question is - Can I use the DTG to generate the dtsi file from defect-detection PL design (.xsa file)? or I need to manual modify the dtsi file generated from DTG?

I used below command to auto generate .dtsi file, I reference this link https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_dtsi_dtbo_generation.html

xsct
hsi open_hw_design /home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_save0307-2021.1.xsa
hsi set_repo_path /home/tonyho/workspace/device-tree-xlnx
hsi create_sw_design device-tree -os device_tree -proc psu_cortexa53_0
hsi set_property CONFIG.dt_overlay true [hsi::get_os]
hsi generate_target -dir save0307-2021.1_xlnx_rel_v2021.1
hsi close_hw_design [hsi::current_hw_design]
exit

Note: the /home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_save0307-2021.1.xsa is the file i build from kv260-vitis and branch = release-2021.1

TonyHo722 commented 2 years ago

I got the answer in this link https://github.com/Xilinx/kv260-firmware/issues/2#issuecomment-1061222718 I need to manual modify the dtsi file generated from DTG to make it work.