Timing error compiling hello_world with kv260_ispMipiRx_vcu_DP platform

[zohourih]

I have built the kv260_ispMipiRx_vcu_DP platform provided in this repository and I am trying to synthesize the hello_world example from the Vitis Accel repository with this platform. However, the build fails with timing errors. This is my command line:

make sd_card TARGET=hw DEVICE=kv260_ispMipiRx_vcu_DP HOST_ARCH=aarch64 EDGE_COMMON_SW=/tools/xilinx/petalinux/2020.2/

And this is the end of the build log:

===>The following messages were generated while  Compiling (bitstream) accelerator binary: vadd Log file: /home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/prj/prj.runs/impl_1/runme.log  :
ERROR: [VPL 101-2] design did not meet timing - Design failed to meet timing.
    Failed timing checks (paths):
        {kv260_ispMipiRx_vcu_DP_i/axi_ic_PS_0_S_AXI_HP1_FPD/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/length_counter_1_reg[1]/C --> kv260_ispMipiRx_vcu_DP_i/axi_ic_PS_0_S_AXI_HP1_FPD/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN}

    Please check the routed checkpoint (dr_routed_timing.dcp) and timing summary report (dr_timing_summary.rpt) for more information.
ERROR: [VPL 101-3] sourcing script /home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/scripts/_full_write_bitstream_pre.tcl failed
ERROR: [VPL 60-773] In '/home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/vivado.log', caught Tcl error:  problem implementing dynamic region, impl_1: write_bitstream ERROR, please look at the run log file '/home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: write_bitstream ERROR, please look at the run log file '/home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [16:37:14] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:09 ; elapsed = 00:17:51 . Memory (MB): peak = 1586.227 ; gain = 0.000 ; free physical = 147385 ; free virtual = 314962
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:141: recipe for target 'build_dir.hw.kv260_ispMipiRx_vcu_DP/vadd.xclbin' failed
make: *** [build_dir.hw.kv260_ispMipiRx_vcu_DP/vadd.xclbin] Error 1

I have attached the timing summary, as well. Am I doing something wrong here?

dr_timing_summary.txt

[chkohn]

The make options that you have listed don't apply to this repo so not sure what exactly you are running. Maybe this is really something that should be posted in the other git repo instead.

I'm not familiar with the accelerator that you are using but timing closure problems can be due to many different things. The examples that are shipped as part of this repo have all been vetted and close timing. So this is really not an "issue" as I can always create a design that does not meet timing on a given device for a given platform.

A few debug pointers:

• Open the generated Vivado design and check what paths have timing errors and how much is it off
• Make sure the accelerator meets timing post HLS synthesis for the target frequency
• Tweak the HLS code if it doesn't meet timing
• Try lowering the accelerator clock frequency
• Reduce the logic footprint of the accelerator
• Try different Vivado implementation strategies
• Check the connectivity of the generated designs and if needed guide the Vitis platform linker what HP ports/interconnects to connect to

[zohourih]

@chkohn Thank you for your reply. I am using the kv260_ispMipiRx_vcu_DP platform from this repository in the standard Vitis acceleration flow, in the same way I have used many other Vitis platforms for both Xilinx MPSoC (e.g. the ones here) and Alveo boards, including custom platforms. As part of the first test before using a new platform, I always synthesize Xilinx's own hello_world example, which is an extremely small and simple design, to make sure the platform works correctly, and I have never experienced timing errors with this simple design with the 10+ platforms I have used across different devices, except this one. If a platform does not meet timing even with the hello_world example, it means it won't meet timing with 99% of other designs, as well, except maybe with custom placement and routing constraints. Chances are, the timing closure of the platform is very tight with little to no slack time, resulting in timing issues with even small designs such as the one I am using.

Can you please clarify if the platforms in this repository are intended to be used with custom kernels in the Vitis acceleration flow, or if they are solely designed to be coupled with the overlays in this repository and Xilinx DPU, purely targeted for development of software applications without changing the platform and PL design?

Edit: Can you please also clarify if these platforms in this repository support Dynamic Function eXchange (DFX), which would further complicate routing from what I understand?

[chkohn]

@zohourih the only advice I can give is to look at the generated Vivado design and analyze it to see why timing is not met. If it's a small kernel, then it should definitely be able to meet timing. Some of the provided examples instantiate a DPU IP and a custom preprocessing accelerator and they meet timing. You can also compare the generated Vivado designs of one of the provided overlays with your kernel, it may give you a clue what's different.

The platforms are definitely meant to be extended with custom kernels but you may need to tweak clock frequency or settings for the vivado linker to achieve optimal results. Each platform comes with one example overlay which can be used as starting point or reference.

None of the provided platforms support DFX today.

[zohourih]

@chkohn Yes, the design is extremely small, and that is why I am surprised it is failing to meet timing. The timing failure is happening with the 300 MHz clock and on the AXI interconnect that is automatically inserted into the design by Vitis to connect the user kernel to HP1. The slack is not too large (-0.040); however, considering the simplicity and small size of the user kernel, even such a small negative slack is quite surprising. I can imagine the designs provided by Xilinx have probably gone through a lot of manual timing tuning, which would incur a lot of burden for normal users if they have to do such thing for even simple and small designs. Nonetheless, I will try to dig deeper and see if I can get around the timing failure.

[chkohn]

@zohourih ok, please share your results here. @sweatharao please chime in here if you have any suggestions.

[sweatharao]

@zohourih can you take a look at this file and use it in your flow https://github.com/Xilinx/kv260-vitis/blob/release-2020.2.2_k26/overlays/examples/smartcam/prj_conf/prj_config_1dpu

• You can either reduce the clock frequency on your kernel under the [clock] section
• Maybe distribute the memory ports across different HP port under the [connectivity] section. This is likely not needed as your bandwidth requirement maybe low.
• Try different implementation strategies under [vivado] the section

[chkohn]

@zohourih can this issue be closed?