Support for allowing direct VEXTRACT to 20-bit registers

Xilinx / llvm-aie

Fork of LLVM to support AMD AIEngine processors

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Support for allowing direct VEXTRACT to 20-bit registers #233

Open abhinay-anubola opened 2 weeks ago

abhinay-anubola commented 2 weeks ago

This update introduces support for direct VEXTRACT to 20-bit registers by adding vextract.8/16/32 intrinsics as source nodes in the s20narrowing pass.
The MachineVerifier has been updated to allow G_AIE_SEXT_EXTRACT_VECTOR_ELT and G_AIE_ZEXT_EXTRACT_VECTOR_ELT to accept 20-bit outputs.
Additionally, tests have been added and updated to reflect these functional changes.

krishnamtibrewala commented 1 week ago

Given that you mentioned there are no QoR gain, I would recommend you to re look at the instruction that consume S20 type reg. Because for the optimization starts to trace back from an instruction that consumes S20 type which might not be captured in isNativeS20Consumer function.