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Xilinx / llvm-aie

Fork of LLVM to support AMD AIEngine processors
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[AIE2] Fix memory access cycle for TM instructions #240

Open katerynamuts opened 2 days ago

katerynamuts commented 2 days ago

Exploring the architecture design, it was found that the instructions that store to and load from the tile memory (TM) map access the TM at cycle 4 instead of cycle 5. This PR changes MemoryCycle in AIE2Schedule.td file from 5 to 4 for such instructions.

The fix changes some tests. After checking the changed tests with @martien-de-jong, it became clear that changing the memory cycle changes the first and last memory cycle for the TM instructions from 5 to 4 which are used in AIEBaseInstrInfo::getConservativeMemoryLatency used in MaxLatencyFinder. As a result, in the tests an additional nop is added because of the worst-case analysis used for inter-block scheduling.

krishnamtibrewala commented 12 hours ago

Hi @katerynamuts did you find this info in the architecture file that you had shared with me a month back ?

katerynamuts commented 8 hours ago

Hi @katerynamuts did you find this info in the architecture file that you had shared with me a month back ?

@krishnamtibrewala yes