data input when generating verilog

[tsp6]

Hello,

I ma trying to understand when generating verilog files, from where does the logicnets take the input data. Is it from DDR memory, If yes where is the memory location of it.

It will be really helpful if I get a clear understanding of how the data is being processed to generate verilog scripts.

Thank You

[nickfraser]

I'm sorry, I don't quite understand the question - could you explain in more detail?

The input data is not used anywhere in the verilog generation process.

[tsp6]

Hello @nickfraser ,

So the logicnets takes the input data and preprosses it , then train, validate and convert lut ot neq and finally generates verilog files and using this verilog files it run synthesis with the help of vivado tool. So after the synthesis, when I try to open rtl or elaborated design of the cybersecurity example I can see the ips of each layer in vlock diagram. In that block diagram I am unable to figure out from where does the network takes the input to be able to demonstrate a use case for cybersecurity example. Beacuse there is only a layers description in the block diagram. So what I am thinking is there should be a memory from where the network takes the input from the docker container and uses it. So, can you please help me understand how it works. Any answers are appriciated.

Thank You

[nickfraser]

Hi @tsp6,

As stated in our paper, the results are all for out-of-context synthesis. This repository doesn't include complete examples to run these designs in hardware. Functional correctness in this repo is performed using verilator.

If you would like to contribute a complete system design to this repository, that would be very welcome. 👍