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Xilinx / logicnets

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Regarding the Hardware implementation of logicnets framework #32

Closed tsp6 closed 1 year ago

tsp6 commented 1 year ago

Hello @nickfraser,

I have tried using this co-desidned framework for my project and was very helpful and informative. Now I can able to run synthesis using logicnets with the help of invoking vivado. As mentioned in the paper about the results showing Accuracy , Model LUT, FF, Synth LUT for differents models like JSC-S, JSC-M, JSC-L and NID-S, NID-M, etc. I want to know on which hardware(FPGA) you have implemented this model. Because I am not sure how this logicnets had implemented directly on hardware. When I try to generate a eloborated design of one of the example I can see the number of layers with neurons, but unable to figure out how the input to this network was given. Could you help me understand in a better way. Any answer is highly appreicated.

Thank You tsp6

nickfraser commented 1 year ago

Hi @tsp6,

I want to know on which hardware(FPGA) you have implemented this model.

As stated in #31, the code in this repo only shows how to reproduce our out-of-context results from our FPL paper. The device used is an Alveo U280.

If you would like to contribute a full system implementation, you're very welcome to.