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Xilinx / logicnets

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Problem with finding final results #42

Closed Masoud071 closed 1 year ago

Masoud071 commented 1 year ago

Hello again; I have problem with finding accuracy, power, delay and other results, especially delay (cycles). It seems that nowhere in code generates delay (cycle). I just found the res.txt file which was brief and not in detail? I would be really thankful if you help me with this.

nickfraser commented 1 year ago

Hi,

See below:

I have problem with finding:

  • accuracy

Accuracy for what? The PyTorch model? The LUT model? The verilog model? If you run the neq2lut.py scripts with the --simulate-pre-synthesis-verilog it will print the accuracy of all models. Reference: 1, 2, 3.

  • power

Power measurement is outside the scope of this repository. I cannot support you for this.

  • delay

Running the neq2lut.py script generates with the --add-registers generates verilog with registers added between each layer. So the cycles = num_layers-1. The relevant code is here. You can verify it by viewing the generated logicnet.v file.

I just found the res.txt file which was brief and not in detail?

If you've run the neq2lut.py script, a vivado project is made under: <log>/verilog/results_logicnet/vivadocompile. You can view the output of your runs there.

nickfraser commented 1 year ago

Closing as stale.