Fix indentation in fpga-manager to avoid warnings

Xilinx / meta-xilinx-tools

Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.

MIT License

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Fix indentation in fpga-manager to avoid warnings #22

Closed Spacefish closed 4 years ago

Spacefish commented 4 years ago

When i build yocto from source i get warning in the build output like:

WARNING: /home/[redacted]/yocto-nightly/build/../meta-xilinx-tools/recipes-bsp/fpga-manager-util/fpga-manager-util_1.0.bb: python should use 4 spaces indentation, but found tabs in fpga-manager-util_1.0.bb, line 124

ckalluri73 commented 4 years ago

please resove the merge conflicts so that I can pull the change in

ckalluri73 commented 4 years ago

Closing the pull request as the current master has the said changes.