fpga-manager-utils recipe looks for pl-final.dts, but pl-final.dts does not exist anymore in xilinx device tree repo

[Xerusial]

https://github.com/Xilinx/meta-xilinx-tools/blob/master/recipes-bsp/fpga-manager-util/fpga-manager-util_1.0.bb#L114

references a pl-final.dts. In the current revision of the xilinx device tree repo: https://github.com/Xilinx/meta-xilinx-tools/blob/master/recipes-bsp/device-tree/device-tree.inc#L6 , this pl-final.dts does not exist anymore. Which dts file should I now use for the base.dtbo?

[Xerusial]

Sorry, I messed up some file origins. The file was from somewhere else. I will keep digging.

[Xerusial]

If anyone stumbles across this: WIth the new xilinx yocto metalayers, fpga-overlay has to be added to MACHINE_FEATURES

[Xerusial]

https://stackoverflow.com/questions/73892571/how-do-i-include-the-base-dtbo-pl-final-dts-for-a-reconfigurable-fpga-in-my-yoct/73892572#73892572

[grsandeep85]

Hi @Xerusial,

Are you using DFx with static and partial xsa? If so then you need to create two recipes one for static xsa and one for partial xsa.

Static XSA recipe template:

#
# This file is the static recipe.
#

SUMMARY = "DFX static firmware using fpgamanager_dtg bbclass"
LICENSE = "MIT"
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"

inherit fpgamanager_dtg

SRC_URI = "\
        file://opendfx-static.xsa \
        file://shell.json \
"

Paritial XSA recipe template:

#
# This file is the opendfx-rp0-aes128 recipe.
#

SUMMARY = "DFX opendfx-rp0-aes128 partial firmware using fpgamanager_dtg_dfx bbclass"
LICENSE = "MIT"
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"

inherit fpgamanager_dtg_dfx

SRC_URI = " \
        file://opendfx-rp0-aes128.xsa \
        file://accel.json \
"

STATIC_PN = "opendfx-static"
RP_NAME = "rp0"

# By default DTG doesn't generate firmware-name property hence we need this workaround solution for 2022.1 release.
do_configure:append() {
    if ls ${B}/${XSCTH_PROJ}*inst_0.dtsi >/dev/null 2>&1; then
        # Workaround solution to add partial firmware name.
        sed -i '/partial-fpga-config/i firmware-name = "${PN}.pdi";' $(ls ${B}/${XSCTH_PROJ}*inst_0.dtsi 2> /dev/null)
    fi
}

If you are not using DFx method and using legacy FPGA Manager(Full Bitstream Loading), then add below variables in local.conf file.

# Specify Vivado XSA path along with xsa name using local file or subversion path
# Add system HDF/XSA
HDF_EXT = "xsa"

# Using local file
HDF_BASE = "file://"
HDF_PATH = "/sandeepg/vivado-workspace/2022.1/zcu102_pl_demo/output/zcu102_pl_demo.xsa"

# ZynqMP Variables for FPGA Manager
MACHINE_FEATURES += "fpga-overlay"
IMAGE_INSTALL:append = "\
    fpga-manager-util \
    fpga-manager-script \
"

[Xerusial]

@grsandeep85 I am using the legacy approach and these variables have all been already added to my local.conf, except the newly required MACHINE_FEATURE fpga-overlay. By adding this additionally, the dtbo was generated again

[grsandeep85]

Hi @Xerusial ,

Yes these variables required to generate DT overlays and package boot.bin to rootfs.

https://github.com/Xilinx/meta-xilinx-tools/blob/xlnx-rel-v2022.1_update2/classes/xsctyaml.bbclass#L62 https://github.com/Xilinx/meta-xilinx-tools/blob/xlnx-rel-v2022.1_update2/recipes-bsp/bootbin/xilinx-bootbin_1.0.bbappend#L1