Xilinx / mlir-aie

An MLIR-based toolchain for AMD AI Engine-enabled devices.
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Trace examples fail after switch to txn ops #1562

Closed fifield closed 2 weeks ago

fifield commented 3 weeks ago

The trace examples use low level npu ops to program shim dmas which means they also need to patch bds with the buffer addresses at runtime using aiex.npu.address_patch, but they are not currently doing this.