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An MLIR-based toolchain for AMD AI Engine-enabled devices.
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`AIE2TargetModel::isLegalMemtileConnection` incorrect for many `Ctrl`, `DMA` and `Trace` port connections #1567

Open makslevental opened 3 weeks ago

makslevental commented 3 weeks ago 
isLegalMemtileConnection wrong (reports true when false): src: Ctrl0, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: Ctrl0, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: Ctrl0, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: Ctrl0, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: Ctrl0, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: DMA0, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: DMA0, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: DMA0, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: DMA0, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: DMA0, dst: DMA5
isLegalMemtileConnection wrong (reports true when false): src: DMA1, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: DMA1, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: DMA1, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: DMA1, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: DMA1, dst: DMA5
isLegalMemtileConnection wrong (reports true when false): src: DMA2, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: DMA2, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: DMA2, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: DMA2, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: DMA2, dst: DMA5
isLegalMemtileConnection wrong (reports true when false): src: DMA3, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: DMA3, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: DMA3, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: DMA3, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: DMA3, dst: DMA5
isLegalMemtileConnection wrong (reports true when false): src: DMA4, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: DMA4, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: DMA4, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: DMA4, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: DMA4, dst: DMA5
isLegalMemtileConnection wrong (reports true when false): src: DMA5, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: DMA5, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: DMA5, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: DMA5, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: DMA5, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: Ctrl0
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: DMA0
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: DMA1
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: DMA2
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: DMA3
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: DMA4
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: North0
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: North1
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: North2
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: North3
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: North4
isLegalMemtileConnection wrong (reports true when false): src: Trace0, dst: North5

See Figure 6-9 in arch spec.